drivers/net/wireless/marvell/libertas/if_spi.h

Source file repositories/reference/linux-study-clean/drivers/net/wireless/marvell/libertas/if_spi.h

File Facts

System
Linux kernel
Corpus path
drivers/net/wireless/marvell/libertas/if_spi.h
Extension
.h
Size
8863 bytes
Lines
203
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _LBS_IF_SPI_H_
#define _LBS_IF_SPI_H_

#define IPFIELD_ALIGN_OFFSET 2
#define IF_SPI_CMD_BUF_SIZE 2400

/***************** Firmware *****************/

#define IF_SPI_FW_NAME_MAX 30

#define MAX_MAIN_FW_LOAD_CRC_ERR 10

/* Chunk size when loading the helper firmware */
#define HELPER_FW_LOAD_CHUNK_SZ 64

/* Value to write to indicate end of helper firmware dnld */
#define FIRMWARE_DNLD_OK 0x0000

/* Value to check once the main firmware is downloaded */
#define SUCCESSFUL_FW_DOWNLOAD_MAGIC 0x88888888

/***************** SPI Interface Unit *****************/
/* Masks used in SPI register read/write operations */
#define IF_SPI_READ_OPERATION_MASK 0x0
#define IF_SPI_WRITE_OPERATION_MASK 0x8000

/* SPI register offsets. 4-byte aligned. */
#define IF_SPI_DEVICEID_CTRL_REG 0x00	/* DeviceID controller reg */
#define IF_SPI_IO_READBASE_REG 0x04 	/* Read I/O base reg */
#define IF_SPI_IO_WRITEBASE_REG 0x08	/* Write I/O base reg */
#define IF_SPI_IO_RDWRPORT_REG 0x0C	/* Read/Write I/O port reg */

#define IF_SPI_CMD_READBASE_REG 0x10	/* Read command base reg */
#define IF_SPI_CMD_WRITEBASE_REG 0x14	/* Write command base reg */
#define IF_SPI_CMD_RDWRPORT_REG 0x18	/* Read/Write command port reg */

#define IF_SPI_DATA_READBASE_REG 0x1C	/* Read data base reg */
#define IF_SPI_DATA_WRITEBASE_REG 0x20	/* Write data base reg */
#define IF_SPI_DATA_RDWRPORT_REG 0x24	/* Read/Write data port reg */

#define IF_SPI_SCRATCH_1_REG 0x28	/* Scratch reg 1 */
#define IF_SPI_SCRATCH_2_REG 0x2C	/* Scratch reg 2 */
#define IF_SPI_SCRATCH_3_REG 0x30	/* Scratch reg 3 */
#define IF_SPI_SCRATCH_4_REG 0x34	/* Scratch reg 4 */

#define IF_SPI_TX_FRAME_SEQ_NUM_REG 0x38 /* Tx frame sequence number reg */
#define IF_SPI_TX_FRAME_STATUS_REG 0x3C	/* Tx frame status reg */

#define IF_SPI_HOST_INT_CTRL_REG 0x40	/* Host interrupt controller reg */

#define IF_SPI_CARD_INT_CAUSE_REG 0x44	/* Card interrupt cause reg */
#define IF_SPI_CARD_INT_STATUS_REG 0x48 /* Card interrupt status reg */
#define IF_SPI_CARD_INT_EVENT_MASK_REG 0x4C /* Card interrupt event mask */
#define IF_SPI_CARD_INT_STATUS_MASK_REG	0x50 /* Card interrupt status mask */

#define IF_SPI_CARD_INT_RESET_SELECT_REG 0x54 /* Card interrupt reset select */

#define IF_SPI_HOST_INT_CAUSE_REG 0x58	/* Host interrupt cause reg */
#define IF_SPI_HOST_INT_STATUS_REG 0x5C	/* Host interrupt status reg */
#define IF_SPI_HOST_INT_EVENT_MASK_REG 0x60 /* Host interrupt event mask */
#define IF_SPI_HOST_INT_STATUS_MASK_REG	0x64 /* Host interrupt status mask */
#define IF_SPI_HOST_INT_RESET_SELECT_REG 0x68 /* Host interrupt reset select */

#define IF_SPI_DELAY_READ_REG 0x6C	/* Delay read reg */
#define IF_SPI_SPU_BUS_MODE_REG 0x70	/* SPU BUS mode reg */

/***************** IF_SPI_DEVICEID_CTRL_REG *****************/
#define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_ID(dc) ((dc & 0xffff0000)>>16)
#define IF_SPI_DEVICEID_CTRL_REG_TO_CARD_REV(dc) (dc & 0x000000ff)

/***************** IF_SPI_HOST_INT_CTRL_REG *****************/
/* Host Interrupt Control bit : Wake up */
#define IF_SPI_HICT_WAKE_UP				(1<<0)
/* Host Interrupt Control bit : WLAN ready */
#define IF_SPI_HICT_WLAN_READY				(1<<1)
/*#define IF_SPI_HICT_FIFO_FIRST_HALF_EMPTY		(1<<2) */
/*#define IF_SPI_HICT_FIFO_SECOND_HALF_EMPTY		(1<<3) */
/*#define IF_SPI_HICT_IRQSRC_WLAN			(1<<4) */
/* Host Interrupt Control bit : Tx auto download */
#define IF_SPI_HICT_TX_DOWNLOAD_OVER_AUTO		(1<<5)
/* Host Interrupt Control bit : Rx auto upload */
#define IF_SPI_HICT_RX_UPLOAD_OVER_AUTO			(1<<6)
/* Host Interrupt Control bit : Command auto download */
#define IF_SPI_HICT_CMD_DOWNLOAD_OVER_AUTO		(1<<7)
/* Host Interrupt Control bit : Command auto upload */
#define IF_SPI_HICT_CMD_UPLOAD_OVER_AUTO		(1<<8)

/***************** IF_SPI_CARD_INT_CAUSE_REG *****************/
/* Card Interrupt Case bit : Tx download over */
#define IF_SPI_CIC_TX_DOWNLOAD_OVER			(1<<0)

Annotation

Implementation Notes