drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

Source file repositories/reference/linux-study-clean/drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h

File Facts

System
Linux kernel
Corpus path
drivers/net/wireless/mediatek/mt76/mt76_connac3_mac.h
Extension
.h
Size
12441 bytes
Lines
401
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __MT76_CONNAC3_MAC_H
#define __MT76_CONNAC3_MAC_H

enum {
	MT_CTX0,
	MT_HIF0 = 0x0,

	MT_LMAC_AC00 = 0x0,
	MT_LMAC_AC01,
	MT_LMAC_AC02,
	MT_LMAC_AC03,
	MT_LMAC_ALTX0 = 0x10,
	MT_LMAC_BMC0,
	MT_LMAC_BCN0,
	MT_LMAC_PSMP0,
};

#define MT_CT_PARSE_LEN			72
#define MT_CT_DMA_BUF_NUM		2

#define MT_RXD0_LENGTH			GENMASK(15, 0)
#define MT_RXD0_PKT_FLAG                GENMASK(19, 16)
#define MT_RXD0_PKT_TYPE		GENMASK(31, 27)

#define MT_RXD0_MESH			BIT(18)
#define MT_RXD0_MHCP			BIT(19)
#define MT_RXD0_NORMAL_ETH_TYPE_OFS	GENMASK(22, 16)

#define MT_RXD0_SW_PKT_TYPE_MASK	GENMASK(31, 16)
#define MT_RXD0_SW_PKT_TYPE_MAP		0x380F
#define MT_RXD0_SW_PKT_TYPE_FRAME	0x3801

/* RXD DW1 */
#define MT_RXD1_NORMAL_WLAN_IDX		GENMASK(11, 0)
#define MT_RXD1_NORMAL_GROUP_1		BIT(16)
#define MT_RXD1_NORMAL_GROUP_2		BIT(17)
#define MT_RXD1_NORMAL_GROUP_3		BIT(18)
#define MT_RXD1_NORMAL_GROUP_4		BIT(19)
#define MT_RXD1_NORMAL_GROUP_5		BIT(20)
#define MT_RXD1_NORMAL_KEY_ID		GENMASK(22, 21)
#define MT_RXD1_NORMAL_CM		BIT(23)
#define MT_RXD1_NORMAL_CLM		BIT(24)
#define MT_RXD1_NORMAL_ICV_ERR		BIT(25)
#define MT_RXD1_NORMAL_TKIP_MIC_ERR	BIT(26)
#define MT_RXD1_NORMAL_BAND_IDX		GENMASK(28, 27)
#define MT_RXD1_NORMAL_SPP_EN		BIT(29)
#define MT_RXD1_NORMAL_ADD_OM		BIT(30)
#define MT_RXD1_NORMAL_SEC_DONE		BIT(31)

/* RXD DW2 */
#define MT_RXD2_NORMAL_BSSID		GENMASK(5, 0)
#define MT_RXD2_NORMAL_MAC_HDR_LEN	GENMASK(12, 8)
#define MT_RXD2_NORMAL_HDR_TRANS	BIT(7)
#define MT_RXD2_NORMAL_HDR_OFFSET	GENMASK(15, 13)
#define MT_RXD2_NORMAL_SEC_MODE		GENMASK(20, 16)
#define MT_RXD2_NORMAL_MU_BAR		BIT(21)
#define MT_RXD2_NORMAL_SW_BIT		BIT(22)
#define MT_RXD2_NORMAL_AMSDU_ERR	BIT(23)
#define MT_RXD2_NORMAL_MAX_LEN_ERROR	BIT(24)
#define MT_RXD2_NORMAL_HDR_TRANS_ERROR	BIT(25)
#define MT_RXD2_NORMAL_INT_FRAME	BIT(26)
#define MT_RXD2_NORMAL_FRAG		BIT(27)
#define MT_RXD2_NORMAL_NULL_FRAME	BIT(28)
#define MT_RXD2_NORMAL_NDATA		BIT(29)
#define MT_RXD2_NORMAL_NON_AMPDU	BIT(30)
#define MT_RXD2_NORMAL_BF_REPORT	BIT(31)

/* RXD DW3 */
#define MT_RXD3_NORMAL_RXV_SEQ		GENMASK(7, 0)
#define MT_RXD3_NORMAL_CH_FREQ		GENMASK(15, 8)
#define MT_RXD3_NORMAL_ADDR_TYPE	GENMASK(17, 16)
#define MT_RXD3_NORMAL_U2M		BIT(0)
#define MT_RXD3_NORMAL_HTC_VLD		BIT(18)
#define MT_RXD3_NORMAL_BEACON_MC	BIT(20)
#define MT_RXD3_NORMAL_BEACON_UC	BIT(21)
#define MT_RXD3_NORMAL_CO_ANT		BIT(22)
#define MT_RXD3_NORMAL_FCS_ERR		BIT(24)
#define MT_RXD3_NORMAL_IP_SUM		BIT(26)
#define MT_RXD3_NORMAL_UDP_TCP_SUM	BIT(27)
#define MT_RXD3_NORMAL_VLAN2ETH		BIT(31)

/* RXD DW4 */
#define MT_RXD4_NORMAL_PAYLOAD_FORMAT	GENMASK(1, 0)
#define MT_RXD4_FIRST_AMSDU_FRAME	GENMASK(1, 0)
#define MT_RXD4_MID_AMSDU_FRAME		BIT(1)
#define MT_RXD4_LAST_AMSDU_FRAME	BIT(0)

#define MT_RXV_HDR_BAND_IDX		BIT(24)

/* RXD GROUP4 */

Annotation

Implementation Notes