drivers/net/wireless/mediatek/mt76/mt7603/mac.h

Source file repositories/reference/linux-study-clean/drivers/net/wireless/mediatek/mt76/mt7603/mac.h

File Facts

System
Linux kernel
Corpus path
drivers/net/wireless/mediatek/mt76/mt7603/mac.h
Extension
.h
Size
8088 bytes
Lines
243
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __MT7603_MAC_H
#define __MT7603_MAC_H

#define MT_RXD0_LENGTH			GENMASK(15, 0)
#define MT_RXD0_PKT_TYPE		GENMASK(31, 29)

#define MT_RXD0_NORMAL_ETH_TYPE_OFS	GENMASK(22, 16)
#define MT_RXD0_NORMAL_IP_SUM		BIT(23)
#define MT_RXD0_NORMAL_UDP_TCP_SUM	BIT(24)
#define MT_RXD0_NORMAL_GROUP_1		BIT(25)
#define MT_RXD0_NORMAL_GROUP_2		BIT(26)
#define MT_RXD0_NORMAL_GROUP_3		BIT(27)
#define MT_RXD0_NORMAL_GROUP_4		BIT(28)

enum rx_pkt_type {
	PKT_TYPE_TXS		= 0,
	PKT_TYPE_TXRXV		= 1,
	PKT_TYPE_NORMAL		= 2,
	PKT_TYPE_RX_DUP_RFB	= 3,
	PKT_TYPE_RX_TMR		= 4,
	PKT_TYPE_RETRIEVE	= 5,
	PKT_TYPE_RX_EVENT	= 7,
};

#define MT_RXD1_NORMAL_BSSID		GENMASK(31, 26)
#define MT_RXD1_NORMAL_PAYLOAD_FORMAT	GENMASK(25, 24)
#define MT_RXD1_NORMAL_HDR_TRANS	BIT(23)
#define MT_RXD1_NORMAL_HDR_OFFSET	BIT(22)
#define MT_RXD1_NORMAL_MAC_HDR_LEN	GENMASK(21, 16)
#define MT_RXD1_NORMAL_CH_FREQ		GENMASK(15, 8)
#define MT_RXD1_NORMAL_KEY_ID		GENMASK(7, 6)
#define MT_RXD1_NORMAL_BEACON_UC	BIT(5)
#define MT_RXD1_NORMAL_BEACON_MC	BIT(4)
#define MT_RXD1_NORMAL_BCAST		BIT(3)
#define MT_RXD1_NORMAL_MCAST		BIT(2)
#define MT_RXD1_NORMAL_U2M		BIT(1)
#define MT_RXD1_NORMAL_HTC_VLD		BIT(0)

#define MT_RXD2_NORMAL_NON_AMPDU	BIT(31)
#define MT_RXD2_NORMAL_NON_AMPDU_SUB	BIT(30)
#define MT_RXD2_NORMAL_NDATA		BIT(29)
#define MT_RXD2_NORMAL_NULL_FRAME	BIT(28)
#define MT_RXD2_NORMAL_FRAG		BIT(27)
#define MT_RXD2_NORMAL_UDF_VALID	BIT(26)
#define MT_RXD2_NORMAL_LLC_MIS		BIT(25)
#define MT_RXD2_NORMAL_MAX_LEN_ERROR	BIT(24)
#define MT_RXD2_NORMAL_AMSDU_ERR	BIT(23)
#define MT_RXD2_NORMAL_LEN_MISMATCH	BIT(22)
#define MT_RXD2_NORMAL_TKIP_MIC_ERR	BIT(21)
#define MT_RXD2_NORMAL_ICV_ERR		BIT(20)
#define MT_RXD2_NORMAL_CLM		BIT(19)
#define MT_RXD2_NORMAL_CM		BIT(18)
#define MT_RXD2_NORMAL_FCS_ERR		BIT(17)
#define MT_RXD2_NORMAL_SW_BIT		BIT(16)
#define MT_RXD2_NORMAL_SEC_MODE		GENMASK(15, 12)
#define MT_RXD2_NORMAL_TID		GENMASK(11, 8)
#define MT_RXD2_NORMAL_WLAN_IDX		GENMASK(7, 0)

#define MT_RXD3_NORMAL_PF_STS		GENMASK(31, 30)
#define MT_RXD3_NORMAL_PF_MODE		BIT(29)
#define MT_RXD3_NORMAL_CLS_BITMAP	GENMASK(28, 19)
#define MT_RXD3_NORMAL_WOL		GENMASK(18, 14)
#define MT_RXD3_NORMAL_MAGIC_PKT	BIT(13)
#define MT_RXD3_NORMAL_OFLD		GENMASK(12, 11)
#define MT_RXD3_NORMAL_CLS		BIT(10)
#define MT_RXD3_NORMAL_PATTERN_DROP	BIT(9)
#define MT_RXD3_NORMAL_TSF_COMPARE_LOSS	BIT(8)
#define MT_RXD3_NORMAL_RXV_SEQ		GENMASK(7, 0)

#define MT_RXV1_VHTA1_B5_B4		GENMASK(31, 30)
#define MT_RXV1_VHTA2_B8_B1		GENMASK(29, 22)
#define MT_RXV1_HT_NO_SOUND		BIT(21)
#define MT_RXV1_HT_SMOOTH		BIT(20)
#define MT_RXV1_HT_SHORT_GI		BIT(19)
#define MT_RXV1_HT_AGGR			BIT(18)
#define MT_RXV1_VHTA1_B22		BIT(17)
#define MT_RXV1_FRAME_MODE		GENMASK(16, 15)
#define MT_RXV1_TX_MODE			GENMASK(14, 12)
#define MT_RXV1_HT_EXT_LTF		GENMASK(11, 10)
#define MT_RXV1_HT_AD_CODE		BIT(9)
#define MT_RXV1_HT_STBC			GENMASK(8, 7)
#define MT_RXV1_TX_RATE			GENMASK(6, 0)

#define MT_RXV2_VHTA1_B16_B6		GENMASK(31, 21)
#define MT_RXV2_LENGTH			GENMASK(20, 0)

#define MT_RXV3_F_AGC1_CAL_GAIN		GENMASK(31, 29)
#define MT_RXV3_F_AGC1_EQ_CAL		BIT(28)
#define MT_RXV3_RCPI1			GENMASK(27, 20)
#define MT_RXV3_F_AGC0_CAL_GAIN		GENMASK(19, 17)

Annotation

Implementation Notes