drivers/net/wireless/mediatek/mt76/mt76x02_dfs.c

File Facts

System

Linux kernel

Corpus path

drivers/net/wireless/mediatek/mt76/mt76x02_dfs.c

Extension

.c

Size

24354 bytes

Lines

893

Domain

Driver Families

Bucket

drivers/net

Inferred role

Driver Families: exported/initcall integration point

Status

integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
• Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
• Allocates kernel memory; connect allocation flags and lifetime to context constraints.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• mt76x02.h

Detected Declarations

• function mt76x02_dfs_set_capture_mode_ctrl
• function mt76x02_dfs_seq_pool_put
• function mt76x02_dfs_seq_pool_get
• function mt76x02_dfs_get_multiple
• function mt76x02_dfs_detector_reset
• function list_for_each_entry_safe
• function mt76x02_dfs_check_chirp
• function mt76x02_dfs_get_hw_pulse
• function mt76x02_dfs_check_hw_pulse
• function mt76x02_dfs_fetch_event
• function mt76x02_dfs_check_event
• function mt76x02_dfs_queue_event
• function mt76x02_dfs_create_sequence
• function mt76x02_dfs_add_event_to_sequence
• function mt76x02_dfs_check_detection
• function list_for_each_entry
• function mt76x02_dfs_add_events
• function mt76x02_dfs_check_event_window
• function mt76x02_dfs_tasklet
• function mt76x02_dfs_init_sw_detector
• function mt76x02_dfs_set_bbp_params
• function mt76x02_phy_dfs_adjust_agc
• function mt76x02_dfs_init_params
• function mt76x02_dfs_init_detector
• function mt76x02_dfs_set_domain
• function mt76x02_regd_notifier
• export mt76x02_phy_dfs_adjust_agc
• export mt76x02_dfs_init_params

Annotated Snippet

if (pulse->engine == 3) {
			ret = mt76x02_dfs_check_chirp(dev);
			break;
		}

		/* check short pulse*/
		if (pulse->w1 < 120)
			ret = (pulse->period >= 2900 &&
			       (pulse->period <= 4700 ||
				pulse->period >= 6400) &&
			       (pulse->period <= 6800 ||
				pulse->period >= 10200) &&
			       pulse->period <= 61600);
		else if (pulse->w1 < 130) /* 120 - 130 */
			ret = (pulse->period >= 2900 &&
			       pulse->period <= 61600);
		else
			ret = (pulse->period >= 3500 &&
			       pulse->period <= 10100);
		break;
	case NL80211_DFS_ETSI:
		if (pulse->engine >= 3)
			break;

		ret = (pulse->period >= 4900 &&
		       (pulse->period <= 10200 ||
			pulse->period >= 12400) &&
		       pulse->period <= 100100);
		break;
	case NL80211_DFS_JP:
		if (dev->mphy.chandef.chan->center_freq >= 5250 &&
		    dev->mphy.chandef.chan->center_freq <= 5350) {
			/* JPW53 */
			if (pulse->w1 <= 130)
				ret = (pulse->period >= 28360 &&
				       (pulse->period <= 28700 ||
					pulse->period >= 76900) &&
				       pulse->period <= 76940);
			break;
		}

		if (pulse->engine > 3)
			break;

		if (pulse->engine == 3) {
			ret = mt76x02_dfs_check_chirp(dev);
			break;
		}

		/* check short pulse*/
		if (pulse->w1 < 120)
			ret = (pulse->period >= 2900 &&
			       (pulse->period <= 4700 ||
				pulse->period >= 6400) &&
			       (pulse->period <= 6800 ||
				pulse->period >= 27560) &&
			       (pulse->period <= 27960 ||
				pulse->period >= 28360) &&
			       (pulse->period <= 28700 ||
				pulse->period >= 79900) &&
			       pulse->period <= 80100);
		else if (pulse->w1 < 130) /* 120 - 130 */
			ret = (pulse->period >= 2900 &&
			       (pulse->period <= 10100 ||
				pulse->period >= 27560) &&
			       (pulse->period <= 27960 ||
				pulse->period >= 28360) &&
			       (pulse->period <= 28700 ||
				pulse->period >= 79900) &&
			       pulse->period <= 80100);
		else
			ret = (pulse->period >= 3900 &&
			       pulse->period <= 10100);
		break;
	case NL80211_DFS_UNSET:
	default:
		return false;
	}

	return ret;
}

static bool mt76x02_dfs_fetch_event(struct mt76x02_dev *dev,
				    struct mt76x02_dfs_event *event)
{
	u32 data;

	/* 1st: DFS_R37[31]: 0 (engine 0) - 1 (engine 2)
	 * 2nd: DFS_R37[21:0]: pulse time
	 * 3rd: DFS_R37[11:0]: pulse width

Annotation

• Immediate include surface: `mt76x02.h`.
• Detected declarations: `function mt76x02_dfs_set_capture_mode_ctrl`, `function mt76x02_dfs_seq_pool_put`, `function mt76x02_dfs_seq_pool_get`, `function mt76x02_dfs_get_multiple`, `function mt76x02_dfs_detector_reset`, `function list_for_each_entry_safe`, `function mt76x02_dfs_check_chirp`, `function mt76x02_dfs_get_hw_pulse`, `function mt76x02_dfs_check_hw_pulse`, `function mt76x02_dfs_fetch_event`.
• Atlas domain: Driver Families / drivers/net.
• Implementation status: integration implementation candidate.
• Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.