drivers/net/wireless/mediatek/mt76/mt7996/regs.h

Source file repositories/reference/linux-study-clean/drivers/net/wireless/mediatek/mt76/mt7996/regs.h

File Facts

System
Linux kernel
Corpus path
drivers/net/wireless/mediatek/mt76/mt7996/regs.h
Extension
.h
Size
28728 bytes
Lines
803
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct __map {
	u32 phys;
	u32 mapped;
	u32 size;
};

struct __base {
	u32 band_base[__MT_MAX_BAND];
};

/* used to differentiate between generations */
struct mt7996_reg_desc {
	const struct __base *base;
	const u32 *offs_rev;
	const struct __map *map;
	u32 map_size;
};

enum base_rev {
	WF_AGG_BASE,
	WF_ARB_BASE,
	WF_TMAC_BASE,
	WF_RMAC_BASE,
	WF_DMA_BASE,
	WF_WTBLOFF_BASE,
	WF_ETBF_BASE,
	WF_LPON_BASE,
	WF_MIB_BASE,
	WF_RATE_BASE,
	__MT_REG_BASE_MAX,
};

#define __BASE(_id, _band)			(dev->reg.base[(_id)].band_base[(_band)])

enum offs_rev {
	MIB_RVSR0,
	MIB_RVSR1,
	MIB_BTSCR5,
	MIB_BTSCR6,
	MIB_RSCR1,
	MIB_RSCR27,
	MIB_RSCR28,
	MIB_RSCR29,
	MIB_RSCR30,
	MIB_RSCR31,
	MIB_RSCR33,
	MIB_RSCR35,
	MIB_RSCR36,
	MIB_BSCR0,
	MIB_BSCR1,
	MIB_BSCR2,
	MIB_BSCR3,
	MIB_BSCR4,
	MIB_BSCR5,
	MIB_BSCR6,
	MIB_BSCR7,
	MIB_BSCR17,
	MIB_TRDR1,
	HIF_REMAP_L1,
	HIF_REMAP_BASE_L1,
	HIF_REMAP_L2,
	HIF_REMAP_BASE_L2,
	CBTOP1_PHY_END,
	INFRA_MCU_END,
	WTBLON_WDUCR,
	WTBL_UPDATE,
	WTBL_ITCR,
	WTBL_ITCR0,
	WTBL_ITCR1,
	__MT_OFFS_MAX,
};

#define __OFFS(id)			(dev->reg.offs_rev[(id)])

/* RRO TOP */
#define MT_RRO_TOP_BASE				0xA000
#define MT_RRO_TOP(ofs)				(MT_RRO_TOP_BASE + (ofs))

#define MT_RRO_BA_BITMAP_BASE0			MT_RRO_TOP(0x8)
#define MT_RRO_BA_BITMAP_BASE1			MT_RRO_TOP(0xC)
#define WF_RRO_AXI_MST_CFG			MT_RRO_TOP(0xB8)
#define WF_RRO_AXI_MST_CFG_DIDX_OK		BIT(12)

#define MT_RRO_ADDR_ARRAY_BASE0			MT_RRO_TOP(0x30)
#define MT_RRO_ADDR_ARRAY_BASE1			MT_RRO_TOP(0x34)
#define MT_RRO_ADDR_ARRAY_ELEM_ADDR_SEG_MODE	BIT(31)

#define MT_RRO_IND_CMD_SIGNATURE_BASE0		MT_RRO_TOP(0x38)
#define MT_RRO_IND_CMD_SIGNATURE_BASE1		MT_RRO_TOP(0x3C)
#define MT_RRO_IND_CMD_0_CTRL0			MT_RRO_TOP(0x40)

Annotation

Implementation Notes