drivers/net/wireless/quantenna/qtnfmac/Makefile
Source file repositories/reference/linux-study-clean/drivers/net/wireless/quantenna/qtnfmac/Makefile
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/wireless/quantenna/qtnfmac/Makefile- Extension
[no extension]- Size
- 500 bytes
- Lines
- 31
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: build/configuration rule
- Status
- atlas-only
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
# SPDX-License-Identifier: GPL-2.0
#
# Copyright (c) 2015-2016 Quantenna Communications, Inc.
# All rights reserved.
#
ccflags-y += \
-Idrivers/net/wireless/quantenna/qtnfmac
obj-$(CONFIG_QTNFMAC) += qtnfmac.o
qtnfmac-objs += \
core.o \
commands.o \
trans.o \
cfg80211.o \
event.o \
util.o \
qlink_util.o
#
obj-$(CONFIG_QTNFMAC_PCIE) += qtnfmac_pcie.o
qtnfmac_pcie-objs += \
shm_ipc.o \
pcie/pcie.o \
pcie/pearl_pcie.o \
pcie/topaz_pcie.o
qtnfmac_pcie-$(CONFIG_DEBUG_FS) += debug.o
Annotation
- Atlas domain: Driver Families / drivers/net.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.