drivers/net/wireless/realtek/rtl8xxxu/8188f.c

Source file repositories/reference/linux-study-clean/drivers/net/wireless/realtek/rtl8xxxu/8188f.c

File Facts

System
Linux kernel
Corpus path
drivers/net/wireless/realtek/rtl8xxxu/8188f.c
Extension
.c
Size
52769 bytes
Lines
1767
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (hw_ctrl) {
			val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
			val32 &= GENMASK(5, 3);
			hw_ctrl_s1 = val32 == BIT(3);
		} else if (sw_ctrl) {
			sw_ctrl_s1 = !(reg948 & BIT(9));
		}

		if (hw_ctrl_s1 || sw_ctrl_s1) {
			initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);

			/* Disable CCK block */
			val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
			val32 &= ~FPGA_RF_MODE_CCK;
			rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);

			val32 = initial_gain & ~OFDM0_X_AGC_CORE1_IGI_MASK;
			val32 |= 0x30;
			rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32);

			/* disable 3-wire */
			rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0);

			/* Setup PSD */
			rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, frequencies[channel]);

			/* Start PSD */
			rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, 0x400000 | frequencies[channel]);

			msleep(30);

			do_notch = rtl8xxxu_read32(priv, REG_FPGA0_PSD_REPORT) >= threshold;

			/* turn off PSD */
			rtl8xxxu_write32(priv, REG_FPGA0_PSD_FUNC, frequencies[channel]);

			/* enable 3-wire */
			rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccc000c0);

			/* Enable CCK block */
			val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
			val32 |= FPGA_RF_MODE_CCK;
			rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);

			rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, initial_gain);

			if (do_notch) {
				rtl8xxxu_write32(priv, REG_OFDM1_CSI_FIX_MASK1, reg_d40[channel]);
				rtl8xxxu_write32(priv, REG_OFDM1_CSI_FIX_MASK2, reg_d44[channel]);
				rtl8xxxu_write32(priv, 0xd48, 0x0);
				rtl8xxxu_write32(priv, 0xd4c, reg_d4c[channel]);

				/* enable CSI mask */
				val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING);
				val32 |= BIT(28);
				rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32);

				return;
			}
		}
	}

	/* disable CSI mask function */
	val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING);
	val32 &= ~BIT(28);
	rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32);
}

static void rtl8188fu_config_channel(struct ieee80211_hw *hw)
{
	struct rtl8xxxu_priv *priv = hw->priv;
	u32 val32;
	u8 channel, subchannel;
	bool sec_ch_above;

	channel = (u8)hw->conf.chandef.chan->hw_value;

	/* Set channel */
	val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
	val32 &= ~MODE_AG_CHANNEL_MASK;
	val32 |= channel;
	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);

	/* Spur calibration */
	rtl8188f_spur_calibration(priv, channel);

	/* Set bandwidth mode */
	val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
	val32 &= ~FPGA_RF_MODE;
	val32 |= hw->conf.chandef.width == NL80211_CHAN_WIDTH_40;

Annotation

Implementation Notes