drivers/net/wireless/realtek/rtl8xxxu/8710b.c

Source file repositories/reference/linux-study-clean/drivers/net/wireless/realtek/rtl8xxxu/8710b.c

File Facts

System
Linux kernel
Corpus path
drivers/net/wireless/realtek/rtl8xxxu/8710b.c
Extension
.c
Size
59141 bytes
Lines
1877
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (priv->vendor_umc) {
			package_type = PACKAGE_QFN48M_U;
		} else if (priv->vendor_smic) {
			package_type = PACKAGE_QFN48M_S;
		} else {
			dev_warn(dev, "The vendor is neither UMC nor SMIC. Assuming the package type is QFN48M_U.\n");

			/*
			 * In this case the vendor driver doesn't set
			 * the package type to anything, which is the
			 * same as setting it to PACKAGE_DEFAULT (0).
			 */
			package_type = PACKAGE_QFN48M_U;
		}
	} else if (package_type != PACKAGE_QFN48M_S &&
		   package_type != PACKAGE_QFN48M_U) {
		dev_warn(dev, "Failed to read the package type. Assuming it's the default QFN48M_U.\n");

		/*
		 * In this case the vendor driver actually sets it to
		 * PACKAGE_DEFAULT, but that selects the same values
		 * from the init tables as PACKAGE_QFN48M_U.
		 */
		package_type = PACKAGE_QFN48M_U;
	}

	priv->package_type = package_type;

	dev_dbg(dev, "Package type: 0x%x\n", package_type);

	cfg2 = rtl8710b_read_syson_reg(priv, REG_SYS_SYSTEM_CFG2_8710B);
	priv->rom_rev = cfg2 & 0xf;

	return rtl8xxxu_config_endpoints_no_sie(priv);
}

static void rtl8710b_revise_cck_tx_psf(struct rtl8xxxu_priv *priv, u8 channel)
{
	if (channel == 13) {
		/* Normal values */
		rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x64B80C1C);
		rtl8xxxu_write32(priv, REG_CCK0_DEBUG_PORT, 0x00008810);
		rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x01235667);
		/* Special value for channel 13 */
		rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xd1d80001);
	} else if (channel == 14) {
		/* Special values for channel 14 */
		rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x0000B81C);
		rtl8xxxu_write32(priv, REG_CCK0_DEBUG_PORT, 0x00000000);
		rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x00003667);
		/* Normal value */
		rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xE82C0001);
	} else {
		/* Restore normal values from the phy init table */
		rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x64B80C1C);
		rtl8xxxu_write32(priv, REG_CCK0_DEBUG_PORT, 0x00008810);
		rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x01235667);
		rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xE82C0001);
	}
}

static void rtl8710bu_config_channel(struct ieee80211_hw *hw)
{
	struct rtl8xxxu_priv *priv = hw->priv;
	bool ht40 = conf_is_ht40(&hw->conf);
	u8 channel, subchannel = 0;
	bool sec_ch_above = 0;
	u32 val32;
	u16 val16;

	channel = (u8)hw->conf.chandef.chan->hw_value;

	if (conf_is_ht40_plus(&hw->conf)) {
		sec_ch_above = 1;
		channel += 2;
		subchannel = 2;
	} else if (conf_is_ht40_minus(&hw->conf)) {
		sec_ch_above = 0;
		channel -= 2;
		subchannel = 1;
	}

	/* Set channel */
	val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
	u32p_replace_bits(&val32, channel, MODE_AG_CHANNEL_MASK);
	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);

	rtl8710b_revise_cck_tx_psf(priv, channel);

	/* Set bandwidth mode */

Annotation

Implementation Notes