drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c
Source file repositories/reference/linux-study-clean/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c- Extension
.c- Size
- 67353 bytes
- Lines
- 2294
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
../wifi.h../pci.h../ps.hreg.hdef.hphy.hrf.hdm.htable.h
Detected Declarations
function rtl88e_phy_query_bb_regfunction rtl88e_phy_set_bb_regfunction rtl88e_phy_query_rf_regfunction rtl88e_phy_set_rf_regfunction _rtl88e_phy_rf_serial_readfunction _rtl88e_phy_rf_serial_writefunction rtl88e_phy_mac_configfunction rtl88e_phy_bb_configfunction rtl88e_phy_rf_configfunction _rtl88e_check_conditionfunction _rtl8188e_config_rf_regfunction _rtl8188e_config_rf_radio_afunction _rtl8188e_config_bb_regfunction _rtl88e_phy_bb8188e_config_parafilefunction _rtl88e_phy_config_mac_with_headerfilefunction handle_branch1function handle_branch2function phy_config_bb_with_headerfilefunction store_pwrindex_rate_offsetfunction phy_config_bb_with_pghdrfunction process_path_afunction rtl88e_phy_config_rf_with_headerfilefunction rtl88e_phy_get_hw_reg_originalvaluefunction _rtl88e_phy_init_bb_rf_register_definitionfunction rtl88e_phy_get_txpower_levelfunction handle_path_afunction _rtl88e_get_txpower_indexfunction _rtl88e_ccxpower_index_checkfunction rtl88e_phy_set_txpower_levelfunction _rtl88e_phy_txpwr_idx_to_dbmfunction rtl88e_phy_scan_operation_backupfunction rtl88e_phy_set_bw_mode_callbackfunction rtl88e_phy_set_bw_modefunction rtl88e_phy_sw_chnl_callbackfunction rtl88e_phy_sw_chnlfunction _rtl88e_phy_sw_chnl_step_by_stepfunction _rtl88e_phy_set_sw_chnl_cmdarrayfunction _rtl88e_phy_path_a_iqkfunction _rtl88e_phy_path_b_iqkfunction _rtl88e_phy_path_a_rx_iqkfunction _rtl88e_phy_path_a_fill_iqk_matrixfunction _rtl88e_phy_save_adda_registersfunction _rtl88e_phy_save_mac_registersfunction _rtl88e_phy_reload_adda_registersfunction _rtl88e_phy_reload_mac_registersfunction _rtl88e_phy_path_adda_onfunction _rtl88e_phy_mac_setting_calibrationfunction _rtl88e_phy_path_a_standby
Annotated Snippet
if (v1 < 0xcdcdcdcd) {
_rtl8188e_config_bb_reg(hw, v1, v2);
} else { /*This line is the start line of branch.*/
/* to protect READ_NEXT_PAIR not overrun */
if (i >= arraylen - 2)
break;
if (!_rtl88e_check_condition(hw, array_table[i])) {
/*Discard the following (offset, data) pairs*/
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < arraylen - 2)
READ_NEXT_PAIR(v1, v2, i);
i -= 2; /* prevent from for-loop += 2*/
} else { /* Configure matched pairs and skip
* to end of if-else.
*/
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < arraylen - 2) {
_rtl8188e_config_bb_reg(hw, v1, v2);
READ_NEXT_PAIR(v1, v2, i);
}
while (v2 != 0xDEAD && i < arraylen - 2)
READ_NEXT_PAIR(v1, v2, i);
}
}
}
}
static void handle_branch2(struct ieee80211_hw *hw, u16 arraylen,
u32 *array_table)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
u32 v1;
u32 v2;
int i;
for (i = 0; i < arraylen; i = i + 2) {
v1 = array_table[i];
v2 = array_table[i+1];
if (v1 < 0xCDCDCDCD) {
rtl_set_bbreg(hw, array_table[i], MASKDWORD,
array_table[i + 1]);
udelay(1);
continue;
} else { /*This line is the start line of branch.*/
/* to protect READ_NEXT_PAIR not overrun */
if (i >= arraylen - 2)
break;
if (!_rtl88e_check_condition(hw, array_table[i])) {
/*Discard the following (offset, data) pairs*/
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < arraylen - 2)
READ_NEXT_PAIR(v1, v2, i);
i -= 2; /* prevent from for-loop += 2*/
} else { /* Configure matched pairs and skip
* to end of if-else.
*/
READ_NEXT_PAIR(v1, v2, i);
while (v2 != 0xDEAD &&
v2 != 0xCDEF &&
v2 != 0xCDCD && i < arraylen - 2) {
rtl_set_bbreg(hw, array_table[i],
MASKDWORD,
array_table[i + 1]);
udelay(1);
READ_NEXT_PAIR(v1, v2, i);
}
while (v2 != 0xDEAD && i < arraylen - 2)
READ_NEXT_PAIR(v1, v2, i);
}
}
rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
"The agctab_array_table[0] is %x Rtl818EEPHY_REGArray[1] is %x\n",
array_table[i], array_table[i + 1]);
}
}
static bool phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
u8 configtype)
{
u32 *array_table;
Annotation
- Immediate include surface: `../wifi.h`, `../pci.h`, `../ps.h`, `reg.h`, `def.h`, `phy.h`, `rf.h`, `dm.h`.
- Detected declarations: `function rtl88e_phy_query_bb_reg`, `function rtl88e_phy_set_bb_reg`, `function rtl88e_phy_query_rf_reg`, `function rtl88e_phy_set_rf_reg`, `function _rtl88e_phy_rf_serial_read`, `function _rtl88e_phy_rf_serial_write`, `function rtl88e_phy_mac_config`, `function rtl88e_phy_bb_config`, `function rtl88e_phy_rf_config`, `function _rtl88e_check_condition`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.