drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h

Source file repositories/reference/linux-study-clean/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h

File Facts

System
Linux kernel
Corpus path
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
Extension
.h
Size
12917 bytes
Lines
290
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __RTL8723E_PWRSEQ_H__
#define __RTL8723E_PWRSEQ_H__

#include "../pwrseqcmd.h"
/* Check document WM-20110607-Paul-RTL8188EE_Power_Architecture-R02.vsd
 *	There are 6 HW Power States:
 *	0: POFF--Power Off
 *	1: PDN--Power Down
 *	2: CARDEMU--Card Emulation
 *	3: ACT--Active Mode
 *	4: LPS--Low Power State
 *	5: SUS--Suspend
 *
 *	The transision from different states are defined below
 *	TRANS_CARDEMU_TO_ACT
 *	TRANS_ACT_TO_CARDEMU
 *	TRANS_CARDEMU_TO_SUS
 *	TRANS_SUS_TO_CARDEMU
 *	TRANS_CARDEMU_TO_PDN
 *	TRANS_ACT_TO_LPS
 *	TRANS_LPS_TO_ACT
 *
 *	TRANS_END
 *	PWR SEQ Version: rtl8188ee_PwrSeq_V09.h
 */

#define	RTL8188EE_TRANS_CARDEMU_TO_ACT_STEPS	10
#define	RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS	10
#define	RTL8188EE_TRANS_CARDEMU_TO_SUS_STEPS	10
#define	RTL8188EE_TRANS_SUS_TO_CARDEMU_STEPS	10
#define	RTL8188EE_TRANS_CARDEMU_TO_PDN_STEPS	10
#define	RTL8188EE_TRANS_PDN_TO_CARDEMU_STEPS	10
#define	RTL8188EE_TRANS_ACT_TO_LPS_STEPS		15
#define	RTL8188EE_TRANS_LPS_TO_ACT_STEPS		15
#define	RTL8188EE_TRANS_END_STEPS		1

/* The following macros have the following format:
 * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value
 *   comments },
 */
#define RTL8188EE_TRANS_CARDEMU_TO_ACT					\
	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)		\
	/* wait till 0x04[17] = 1    power ready*/},			\
	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0)|BIT(1), 0		\
	/* 0x02[1:0] = 0	reset BB*/},				\
	{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)			\
	/*0x24[23] = 2b'01 schmit trigger */},				\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0			\
	/* 0x04[15] = 0 disable HWPDN (control by DRV)*/},		\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4)|BIT(3), 0		\
	/*0x04[12:11] = 2b'00 disable WL suspend*/},			\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)			\
	/*0x04[8] = 1 polling until return 0*/},			\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0			\
	/*wait till 0x04[8] = 0*/},					\
	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0			\
	/*LDO normal mode*/},						\
	{0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,	\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)			\
	/*SDIO Driving*/},

#define RTL8188EE_TRANS_ACT_TO_CARDEMU					\
	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0			\
	/*0x1F[7:0] = 0 turn off RF*/},					\
	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)			\
	/*LDO Sleep mode*/},						\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)			\
	/*0x04[9] = 1 turn off MAC by HW state machine*/},		\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,	\
	PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0			\
	/*wait till 0x04[9] = 0 polling until return 0 to disable*/},

#define RTL8188EE_TRANS_CARDEMU_TO_SUS					\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
	PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,				\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)		\
	/*0x04[12:11] = 2b'01enable WL suspend*/},			\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,	\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)|BIT(4)	\

Annotation

Implementation Notes