drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c

Source file repositories/reference/linux-study-clean/drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c

File Facts

System
Linux kernel
Corpus path
drivers/net/wireless/realtek/rtlwifi/rtl8192d/fw_common.c
Extension
.c
Size
9960 bytes
Lines
371
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (rtlhal->interfaceindex == 0) {
			if (rtl_read_byte(rtlpriv, FW_MAC0_READY) &
			    MAC0_READY) {
				rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG,
					"Polling FW ready success!! REG_MCUFWDL: 0x%x\n",
					rtl_read_byte(rtlpriv,
						      FW_MAC0_READY));
				return 0;
			}
			udelay(5);
		} else {
			if (rtl_read_byte(rtlpriv, FW_MAC1_READY) &
			    MAC1_READY) {
				rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG,
					"Polling FW ready success!! REG_MCUFWDL: 0x%x\n",
					rtl_read_byte(rtlpriv,
						      FW_MAC1_READY));
				return 0;
			}
			udelay(5);
		}
	} while (counter++ < POLLING_READY_TIMEOUT_COUNT);

	if (rtlhal->interfaceindex == 0) {
		rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG,
			"Polling FW ready fail!! MAC0 FW init not ready: 0x%x\n",
			rtl_read_byte(rtlpriv, FW_MAC0_READY));
	} else {
		rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG,
			"Polling FW ready fail!! MAC1 FW init not ready: 0x%x\n",
			rtl_read_byte(rtlpriv, FW_MAC1_READY));
	}
	rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG,
		"Polling FW ready fail!! REG_MCUFWDL:0x%08x\n",
		rtl_read_dword(rtlpriv, REG_MCUFWDL));
	return -1;
}
EXPORT_SYMBOL_GPL(rtl92d_fw_init);

static bool _rtl92d_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum)
{
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	u8 val_hmetfr;
	bool result = false;

	val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR);
	if (((val_hmetfr >> boxnum) & BIT(0)) == 0)
		result = true;
	return result;
}

void rtl92d_fill_h2c_cmd(struct ieee80211_hw *hw,
			 u8 element_id, u32 cmd_len, u8 *cmdbuffer)
{
	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	u8 boxcontent[4], boxextcontent[2];
	u16 box_reg = 0, box_extreg = 0;
	u8 wait_writeh2c_limit = 100;
	bool bwrite_success = false;
	u8 wait_h2c_limit = 100;
	u32 h2c_waitcounter = 0;
	bool isfw_read = false;
	unsigned long flag;
	u8 u1b_tmp;
	u8 boxnum;
	u8 idx;

	if (ppsc->rfpwr_state == ERFOFF || ppsc->inactive_pwrstate == ERFOFF) {
		rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
			"Return as RF is off!!!\n");
		return;
	}

	rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "come in\n");

	while (true) {
		spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
		if (rtlhal->h2c_setinprogress) {
			rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
				"H2C set in progress! Wait to set..element_id(%d)\n",
				element_id);

			while (rtlhal->h2c_setinprogress) {
				spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock,
						       flag);
				h2c_waitcounter++;
				rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
					"Wait 100 us (%d times)...\n",

Annotation

Implementation Notes