drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c
Source file repositories/reference/linux-study-clean/drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/wireless/realtek/rtlwifi/rtl8192d/hw_common.c- Extension
.c- Size
- 35364 bytes
- Lines
- 1226
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
../wifi.h../base.h../cam.h../efuse.h../pci.h../regd.hdef.hreg.hdm_common.hfw_common.hhw_common.hphy_common.h
Detected Declarations
function rtl92d_stop_tx_beaconfunction rtl92d_resume_tx_beaconfunction rtl92d_get_hw_regfunction rtl92d_set_hw_regfunction rtl92d_llt_writefunction rtl92d_enable_hw_security_configfunction rtl92d_set_qosfunction _rtl92d_read_chip_versionfunction _rtl92d_readpowervalue_frompromfunction _rtl92d_read_txpower_infofunction _rtl92d_read_macphymode_from_promfunction _rtl92d_read_macphymode_and_bandtypefunction _rtl92d_efuse_update_chip_versionfunction _rtl92d_read_adapter_infofunction rtl92d_read_eeprom_infofunction rtl92d_update_hal_rate_tablefunction rtl92d_update_hal_rate_maskfunction rtl92d_update_hal_rate_tblfunction rtl92d_update_channel_access_settingfunction rtl92d_gpio_radio_on_off_checkingfunction rtl92d_set_keyexport rtl92d_stop_tx_beaconexport rtl92d_resume_tx_beaconexport rtl92d_get_hw_regexport rtl92d_set_hw_regexport rtl92d_llt_writeexport rtl92d_enable_hw_security_configexport rtl92d_set_qosexport rtl92d_read_eeprom_infoexport rtl92d_update_hal_rate_tblexport rtl92d_update_channel_access_settingexport rtl92d_gpio_radio_on_off_checkingexport rtl92d_set_key
Annotated Snippet
if (rfstate == ERFOFF) {
*((bool *)(val)) = true;
} else {
val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
val_rcr &= 0x00070000;
if (val_rcr)
*((bool *)(val)) = false;
else
*((bool *)(val)) = true;
}
break;
}
case HW_VAR_FW_PSMODE_STATUS:
*((bool *)(val)) = ppsc->fw_current_inpsmode;
break;
case HW_VAR_CORRECT_TSF:{
u64 tsf;
u32 *ptsf_low = (u32 *)&tsf;
u32 *ptsf_high = ((u32 *)&tsf) + 1;
*ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
*ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
*((u64 *)(val)) = tsf;
break;
}
case HW_VAR_INT_MIGRATION:
*((bool *)(val)) = rtlpriv->dm.interrupt_migration;
break;
case HW_VAR_INT_AC:
*((bool *)(val)) = rtlpriv->dm.disable_tx_int;
break;
case HAL_DEF_WOWLAN:
break;
default:
pr_err("switch case %#x not processed\n", variable);
break;
}
}
EXPORT_SYMBOL_GPL(rtl92d_get_hw_reg);
void rtl92d_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
u8 idx;
switch (variable) {
case HW_VAR_ETHER_ADDR:
for (idx = 0; idx < ETH_ALEN; idx++) {
rtl_write_byte(rtlpriv, (REG_MACID + idx),
val[idx]);
}
break;
case HW_VAR_BASIC_RATE: {
u16 rate_cfg = ((u16 *)val)[0];
u8 rate_index = 0;
rate_cfg = rate_cfg & 0x15f;
if (mac->vendor == PEER_CISCO &&
((rate_cfg & 0x150) == 0))
rate_cfg |= 0x01;
rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
rtl_write_byte(rtlpriv, REG_RRSR + 1,
(rate_cfg >> 8) & 0xff);
while (rate_cfg > 0x1) {
rate_cfg = (rate_cfg >> 1);
rate_index++;
}
if (rtlhal->fw_version > 0xe)
rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
rate_index);
break;
}
case HW_VAR_BSSID:
for (idx = 0; idx < ETH_ALEN; idx++) {
rtl_write_byte(rtlpriv, (REG_BSSID + idx),
val[idx]);
}
break;
case HW_VAR_SIFS:
rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
if (!mac->ht_enable)
rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
0x0e0e);
Annotation
- Immediate include surface: `../wifi.h`, `../base.h`, `../cam.h`, `../efuse.h`, `../pci.h`, `../regd.h`, `def.h`, `reg.h`.
- Detected declarations: `function rtl92d_stop_tx_beacon`, `function rtl92d_resume_tx_beacon`, `function rtl92d_get_hw_reg`, `function rtl92d_set_hw_reg`, `function rtl92d_llt_write`, `function rtl92d_enable_hw_security_config`, `function rtl92d_set_qos`, `function _rtl92d_read_chip_version`, `function _rtl92d_readpowervalue_fromprom`, `function _rtl92d_read_txpower_info`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: integration implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.