drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.c

Source file repositories/reference/linux-study-clean/drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.c

File Facts

System
Linux kernel
Corpus path
drivers/net/wireless/realtek/rtlwifi/rtl8192de/dm.c
Extension
.c
Size
5712 bytes
Lines
185
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (mac->opmode == NL80211_IFTYPE_ADHOC) {
			undec_sm_pwdb =
			    rtlpriv->dm.UNDEC_SM_PWDB;
			rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
				"IBSS Client PWDB = 0x%lx\n",
				undec_sm_pwdb);
		} else {
			undec_sm_pwdb =
			    rtlpriv->dm.undec_sm_pwdb;
			rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
				"STA Default Port PWDB = 0x%lx\n",
				undec_sm_pwdb);
		}
	} else {
		undec_sm_pwdb =
		    rtlpriv->dm.UNDEC_SM_PWDB;

		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
			"AP Ext Port PWDB = 0x%lx\n",
			undec_sm_pwdb);
	}
	if (rtlhal->current_bandtype == BAND_ON_5G) {
		if (undec_sm_pwdb >= 0x33) {
			rtlpriv->dm.dynamic_txhighpower_lvl =
						 TXHIGHPWRLEVEL_LEVEL2;
			rtl_dbg(rtlpriv, COMP_HIPWR, DBG_LOUD,
				"5G:TxHighPwrLevel_Level2 (TxPwr=0x0)\n");
		} else if ((undec_sm_pwdb < 0x33)
			   && (undec_sm_pwdb >= 0x2b)) {
			rtlpriv->dm.dynamic_txhighpower_lvl =
						 TXHIGHPWRLEVEL_LEVEL1;
			rtl_dbg(rtlpriv, COMP_HIPWR, DBG_LOUD,
				"5G:TxHighPwrLevel_Level1 (TxPwr=0x10)\n");
		} else if (undec_sm_pwdb < 0x2b) {
			rtlpriv->dm.dynamic_txhighpower_lvl =
						 TXHIGHPWRLEVEL_NORMAL;
			rtl_dbg(rtlpriv, COMP_HIPWR, DBG_LOUD,
				"5G:TxHighPwrLevel_Normal\n");
		}
	} else {
		if (undec_sm_pwdb >=
		    TX_POWER_NEAR_FIELD_THRESH_LVL2) {
			rtlpriv->dm.dynamic_txhighpower_lvl =
						 TXHIGHPWRLEVEL_LEVEL2;
			rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
				"TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n");
		} else
		    if ((undec_sm_pwdb <
			 (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3))
			&& (undec_sm_pwdb >=
			    TX_POWER_NEAR_FIELD_THRESH_LVL1)) {

			rtlpriv->dm.dynamic_txhighpower_lvl =
						 TXHIGHPWRLEVEL_LEVEL1;
			rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
				"TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n");
		} else if (undec_sm_pwdb <
			   (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
			rtlpriv->dm.dynamic_txhighpower_lvl =
						 TXHIGHPWRLEVEL_NORMAL;
			rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
				"TXHIGHPWRLEVEL_NORMAL\n");
		}
	}
	if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
		rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
			"PHY_SetTxPowerLevel8192S() Channel = %d\n",
			rtlphy->current_channel);
		rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
	}
	rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
}

static void rtl92d_dm_pwdb_monitor(struct ieee80211_hw *hw)
{
	struct rtl_priv *rtlpriv = rtl_priv(hw);

	/* AP & ADHOC & MESH will return tmp */
	if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION)
		return;
	/* Indicate Rx signal strength to FW. */
	if (rtlpriv->dm.useramask) {
		u32 temp = rtlpriv->dm.undec_sm_pwdb;

		temp <<= 16;
		temp |= 0x100;
		/* fw v12 cmdid 5:use max macid ,for nic ,
		 * default macid is 0 ,max macid is 1 */
		rtl92d_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, (u8 *) (&temp));
	} else {

Annotation

Implementation Notes