drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c

Source file repositories/reference/linux-study-clean/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c

File Facts

System
Linux kernel
Corpus path
drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c
Extension
.c
Size
91087 bytes
Lines
2727
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (rtlhal->current_bandtype == BAND_ON_2_4G) {
			agctab_arraylen = AGCTAB_2G_ARRAYLENGTH;
			agctab_array_table = rtl8192de_agctab_2garray;
			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
				" ===> phy:MAC1, Rtl819XAGCTAB_2GArray\n");
		} else {
			agctab_5garraylen = AGCTAB_5G_ARRAYLENGTH;
			agctab_5garray_table = rtl8192de_agctab_5garray;
			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
				" ===> phy:MAC1, Rtl819XAGCTAB_5GArray\n");

		}
	}
	phy_reg_arraylen = PHY_REG_2T_ARRAYLENGTH;
	phy_regarray_table = rtl8192de_phy_reg_2tarray;
	rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
		" ===> phy:Rtl819XPHY_REG_Array_PG\n");
	if (configtype == BASEBAND_CONFIG_PHY_REG) {
		for (i = 0; i < phy_reg_arraylen; i = i + 2) {
			rtl_addr_delay(phy_regarray_table[i]);
			rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
				      phy_regarray_table[i + 1]);
			udelay(1);
			rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
				"The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
				phy_regarray_table[i],
				phy_regarray_table[i + 1]);
		}
	} else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
		if (rtlhal->interfaceindex == 0) {
			for (i = 0; i < agctab_arraylen; i = i + 2) {
				rtl_set_bbreg(hw, agctab_array_table[i],
					MASKDWORD,
					agctab_array_table[i + 1]);
				/* Add 1us delay between BB/RF register
				 * setting. */
				udelay(1);
				rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
					"The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
					agctab_array_table[i],
					agctab_array_table[i + 1]);
			}
			rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
				"Normal Chip, MAC0, load Rtl819XAGCTAB_Array\n");
		} else {
			if (rtlhal->current_bandtype == BAND_ON_2_4G) {
				for (i = 0; i < agctab_arraylen; i = i + 2) {
					rtl_set_bbreg(hw, agctab_array_table[i],
						MASKDWORD,
						agctab_array_table[i + 1]);
					/* Add 1us delay between BB/RF register
					 * setting. */
					udelay(1);
					rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
						"The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
						agctab_array_table[i],
						agctab_array_table[i + 1]);
				}
				rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
					"Load Rtl819XAGCTAB_2GArray\n");
			} else {
				for (i = 0; i < agctab_5garraylen; i = i + 2) {
					rtl_set_bbreg(hw,
						agctab_5garray_table[i],
						MASKDWORD,
						agctab_5garray_table[i + 1]);
					/* Add 1us delay between BB/RF registeri
					 * setting. */
					udelay(1);
					rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
						"The Rtl819XAGCTAB_5GArray_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n",
						agctab_5garray_table[i],
						agctab_5garray_table[i + 1]);
				}
				rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
					"Load Rtl819XAGCTAB_5GArray\n");
			}
		}
	}
	return true;
}

static bool _rtl92d_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
	u8 configtype)
{
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	int i;
	u32 *phy_regarray_table_pg;
	u16 phy_regarray_pg_len;

Annotation

Implementation Notes