drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h

Source file repositories/reference/linux-study-clean/drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h

File Facts

System
Linux kernel
Corpus path
drivers/net/wireless/realtek/rtlwifi/rtl8192se/reg.h
Extension
.h
Size
31691 bytes
Lines
1144
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __REALTEK_92S_REG_H__
#define __REALTEK_92S_REG_H__

/* 1. System Configuration Registers  */
#define	REG_SYS_ISO_CTRL			0x0000
#define	REG_SYS_FUNC_EN				0x0002
#define	PMC_FSM					0x0004
#define	SYS_CLKR				0x0008
#define	EPROM_CMD				0x000A
#define	EE_VPD					0x000C
#define	AFE_MISC				0x0010
#define	SPS0_CTRL				0x0011
#define	SPS1_CTRL				0x0018
#define	RF_CTRL					0x001F
#define	LDOA15_CTRL				0x0020
#define	LDOV12D_CTRL				0x0021
#define	LDOHCI12_CTRL				0x0022
#define	LDO_USB_SDIO				0x0023
#define	LPLDO_CTRL				0x0024
#define	AFE_XTAL_CTRL				0x0026
#define	AFE_PLL_CTRL				0x0028
#define	REG_EFUSE_CTRL				0x0030
#define	REG_EFUSE_TEST				0x0034
#define	PWR_DATA				0x0038
#define	DBG_PORT				0x003A
#define	DPS_TIMER				0x003C
#define	RCLK_MON				0x003E

/* 2. Command Control Registers	  */
#define	CMDR					0x0040
#define	TXPAUSE					0x0042
#define	LBKMD_SEL				0x0043
#define	TCR					0x0044
#define	RCR					0x0048
#define	MSR					0x004C
#define	SYSF_CFG				0x004D
#define	RX_PKY_LIMIT				0x004E
#define	MBIDCTRL				0x004F

/* 3. MACID Setting Registers	 */
#define	MACIDR					0x0050
#define	MACIDR0					0x0050
#define	MACIDR4					0x0054
#define	BSSIDR					0x0058
#define	HWVID					0x005E
#define	MAR					0x0060
#define	MBIDCAMCONTENT				0x0068
#define	MBIDCAMCFG				0x0070
#define	BUILDTIME				0x0074
#define	BUILDUSER				0x0078

#define	IDR0					MACIDR0
#define	IDR4					MACIDR4

/* 4. Timing Control Registers	 */
#define	TSFR					0x0080
#define	SLOT_TIME				0x0089
#define	USTIME					0x008A
#define	SIFS_CCK				0x008C
#define	SIFS_OFDM				0x008E
#define	PIFS_TIME				0x0090
#define	ACK_TIMEOUT				0x0091
#define	EIFSTR					0x0092
#define	BCN_INTERVAL				0x0094
#define	ATIMWND					0x0096
#define	BCN_DRV_EARLY_INT			0x0098
#define	BCN_DMATIME				0x009A
#define	BCN_ERR_THRESH				0x009C
#define	MLT					0x009D
#define	RSVD_MAC_TUNE_US			0x009E

/* 5. FIFO Control Registers	  */
#define RQPN					0x00A0
#define	RQPN1					0x00A0
#define	RQPN2					0x00A1
#define	RQPN3					0x00A2
#define	RQPN4					0x00A3
#define	RQPN5					0x00A4
#define	RQPN6					0x00A5
#define	RQPN7					0x00A6
#define	RQPN8					0x00A7
#define	RQPN9					0x00A8
#define	RQPN10					0x00A9
#define	LD_RQPN					0x00AB
#define	RXFF_BNDY				0x00AC
#define	RXRPT_BNDY				0x00B0
#define	TXPKTBUF_PGBNDY				0x00B4
#define	PBP					0x00B5
#define	RXDRVINFO_SZ				0x00B6
#define	TXFF_STATUS				0x00B7

Annotation

Implementation Notes