drivers/net/wireless/realtek/rtlwifi/rtl8821ae/dm.h

Source file repositories/reference/linux-study-clean/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/dm.h

File Facts

System: Linux kernel
Corpus path: drivers/net/wireless/realtek/rtlwifi/rtl8821ae/dm.h
Extension: .h
Size: 9460 bytes
Lines: 294
Domain: Driver Families
Bucket: drivers/net
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

enum FAT_STATE
enum tag_dynamic_init_gain_operation_type_definition
enum dm_1r_cca_e
enum dm_rf_e
enum dm_sw_ant_switch_e
enum pwr_track_control_method

Annotated Snippet

#ifndef	__RTL8821AE_DM_H__
#define __RTL8821AE_DM_H__

#define	MAIN_ANT	0
#define	AUX_ANT	1
#define	MAIN_ANT_CG_TRX	1
#define	AUX_ANT_CG_TRX	0
#define	MAIN_ANT_CGCS_RX	0
#define	AUX_ANT_CGCS_RX	1

#define	TXSCALE_TABLE_SIZE 37

/*RF REG LIST*/
#define	DM_REG_RF_MODE_11N				0x00
#define	DM_REG_RF_0B_11N				0x0B
#define	DM_REG_CHNBW_11N				0x18
#define	DM_REG_T_METER_11N				0x24
#define	DM_REG_RF_25_11N				0x25
#define	DM_REG_RF_26_11N				0x26
#define	DM_REG_RF_27_11N				0x27
#define	DM_REG_RF_2B_11N				0x2B
#define	DM_REG_RF_2C_11N				0x2C
#define	DM_REG_RXRF_A3_11N				0x3C
#define	DM_REG_T_METER_92D_11N			0x42
#define	DM_REG_T_METER_88E_11N			0x42

/*BB REG LIST*/
/*PAGE 8 */
#define	DM_REG_BB_CTRL_11N				0x800
#define	DM_REG_RF_PIN_11N				0x804
#define	DM_REG_PSD_CTRL_11N				0x808
#define	DM_REG_TX_ANT_CTRL_11N			0x80C
#define	DM_REG_BB_PWR_SAV5_11N			0x818
#define	DM_REG_CCK_RPT_FORMAT_11N		0x824
#define	DM_REG_RX_DEFUALT_A_11N		0x858
#define	DM_REG_RX_DEFUALT_B_11N		0x85A
#define	DM_REG_BB_PWR_SAV3_11N			0x85C
#define	DM_REG_ANTSEL_CTRL_11N			0x860
#define	DM_REG_RX_ANT_CTRL_11N			0x864
#define	DM_REG_PIN_CTRL_11N				0x870
#define	DM_REG_BB_PWR_SAV1_11N			0x874
#define	DM_REG_ANTSEL_PATH_11N			0x878
#define	DM_REG_BB_3WIRE_11N			0x88C
#define	DM_REG_SC_CNT_11N				0x8C4
#define	DM_REG_PSD_DATA_11N			0x8B4
/*PAGE 9*/
#define	DM_REG_ANT_MAPPING1_11N		0x914
#define	DM_REG_ANT_MAPPING2_11N		0x918
/*PAGE A*/
#define	DM_REG_CCK_ANTDIV_PARA1_11N	0xA00
#define	DM_REG_CCK_CCA_11N			0xA0A
#define	DM_REG_CCK_CCA_11AC			0xA0A
#define	DM_REG_CCK_ANTDIV_PARA2_11N	0xA0C
#define	DM_REG_CCK_ANTDIV_PARA3_11N	0xA10
#define	DM_REG_CCK_ANTDIV_PARA4_11N	0xA14
#define	DM_REG_CCK_FILTER_PARA1_11N	0xA22
#define	DM_REG_CCK_FILTER_PARA2_11N	0xA23
#define	DM_REG_CCK_FILTER_PARA3_11N	0xA24
#define	DM_REG_CCK_FILTER_PARA4_11N	0xA25
#define	DM_REG_CCK_FILTER_PARA5_11N	0xA26
#define	DM_REG_CCK_FILTER_PARA6_11N	0xA27
#define	DM_REG_CCK_FILTER_PARA7_11N	0xA28
#define	DM_REG_CCK_FILTER_PARA8_11N	0xA29
#define	DM_REG_CCK_FA_RST_11N			0xA2C
#define	DM_REG_CCK_FA_MSB_11N			0xA58
#define	DM_REG_CCK_FA_LSB_11N			0xA5C
#define	DM_REG_CCK_CCA_CNT_11N			0xA60
#define	DM_REG_BB_PWR_SAV4_11N			0xA74
/*PAGE B */
#define	DM_REG_LNA_SWITCH_11N			0XB2C
#define	DM_REG_PATH_SWITCH_11N			0XB30
#define	DM_REG_RSSI_CTRL_11N			0XB38
#define	DM_REG_CONFIG_ANTA_11N			0XB68
#define	DM_REG_RSSI_BT_11N				0XB9C
/*PAGE C */
#define	DM_REG_OFDM_FA_HOLDC_11N		0xC00
#define	DM_REG_RX_PATH_11N				0xC04
#define	DM_REG_TRMUX_11N				0xC08
#define	DM_REG_OFDM_FA_RSTC_11N		0xC0C
#define	DM_REG_RXIQI_MATRIX_11N		0xC14
#define	DM_REG_TXIQK_MATRIX_LSB1_11N	0xC4C
#define	DM_REG_IGI_A_11N				0xC50
#define	DM_REG_IGI_A_11AC				0xC50
#define	DM_REG_ANTDIV_PARA2_11N		0xC54
#define	DM_REG_IGI_B_11N					0xC58
#define	DM_REG_IGI_B_11AC					0xE50
#define	DM_REG_ANTDIV_PARA3_11N		0xC5C
#define	DM_REG_BB_PWR_SAV2_11N			0xC70
#define	DM_REG_RX_OFF_11N				0xC7C
#define	DM_REG_TXIQK_MATRIXA_11N		0xC80

Annotation

Detected declarations: `enum FAT_STATE`, `enum tag_dynamic_init_gain_operation_type_definition`, `enum dm_1r_cca_e`, `enum dm_rf_e`, `enum dm_sw_ant_switch_e`, `enum pwr_track_control_method`.
Atlas domain: Driver Families / drivers/net.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.