drivers/net/wireless/realtek/rtw88/reg.h

Source file repositories/reference/linux-study-clean/drivers/net/wireless/realtek/rtw88/reg.h

File Facts

System
Linux kernel
Corpus path
drivers/net/wireless/realtek/rtw88/reg.h
Extension
.h
Size
32502 bytes
Lines
1005
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __RTW_REG_DEF_H__
#define __RTW_REG_DEF_H__

#define REG_SYS_FUNC_EN		0x0002
#define BIT_FEN_EN_25_1		BIT(13)
#define BIT_FEN_ELDR		BIT(12)
#define BIT_FEN_PCIEA		BIT(6)
#define BIT_FEN_CPUEN		BIT(2)
#define BIT_FEN_USBA		BIT(2)
#define BIT_FEN_BB_GLB_RST	BIT(1)
#define BIT_FEN_BB_RSTB		BIT(0)
#define BIT_R_DIS_PRST		BIT(6)
#define BIT_WLOCK_1C_B6		BIT(5)
#define REG_SYS_PW_CTRL		0x0004
#define BIT_PFM_WOWL		BIT(3)
#define BIT_APFM_OFFMAC		BIT(9)
#define REG_APS_FSMCO		0x0004
#define APS_FSMCO_MAC_ENABLE	BIT(8)
#define APS_FSMCO_MAC_OFF	BIT(9)
#define APS_FSMCO_HW_POWERDOWN	BIT(15)
#define REG_SYS_CLK_CTRL	0x0008
#define BIT_CPU_CLK_EN		BIT(14)

#define REG_SYS_CLKR		0x0008
#define BIT_ANA8M		BIT(1)
#define BIT_WAKEPAD_EN		BIT(3)
#define BIT_LOADER_CLK_EN	BIT(5)

#define REG_RSV_CTRL		0x001C
#define DISABLE_PI		0x3
#define ENABLE_PI		0x2
#define BITS_RFC_DIRECT		(BIT(31) | BIT(30))
#define BIT_WLMCU_IOIF		BIT(0)
#define REG_RF_CTRL		0x001F
#define BIT_RF_SDM_RSTB		BIT(2)
#define BIT_RF_RSTB		BIT(1)
#define BIT_RF_EN		BIT(0)

#define REG_RF_CTRL1		0x0020
#define REG_RF_CTRL2		0x0021

#define REG_AFE_CTRL1		0x0024
#define BIT_MAC_CLK_SEL		(BIT(20) | BIT(21))
#define REG_EFUSE_CTRL		0x0030
#define BIT_EF_FLAG		BIT(31)
#define BIT_SHIFT_EF_ADDR	8
#define BIT_MASK_EF_ADDR	0x3ff
#define BIT_MASK_EF_DATA	0xff
#define BITS_EF_ADDR		(BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR)
#define BITS_PLL		0xf0

#define REG_AFE_XTAL_CTRL	0x24
#define REG_AFE_PLL_CTRL	0x28
#define REG_AFE_CTRL3		0x2c
#define BIT_MASK_XTAL		0x00FFF000
#define BIT_XTAL_GMP_BIT4	BIT(28)

#define REG_LDO_EFUSE_CTRL	0x0034
#define BIT_MASK_EFUSE_BANK_SEL	(BIT(8) | BIT(9))

#define BIT_LDO25_VOLTAGE_V25	0x03
#define BIT_MASK_LDO25_VOLTAGE	GENMASK(6, 4)
#define BIT_SHIFT_LDO25_VOLTAGE	4
#define BIT_LDO25_EN		BIT(7)

#define REG_ACLK_MON		0x3e

#define REG_GPIO_MUXCFG		0x0040
#define BIT_FSPI_EN		BIT(19)
#define BIT_EN_SIC		BIT(12)

#define BIT_PO_BT_PTA_PINS	BIT(9)
#define BIT_BT_PTA_EN		BIT(5)
#define BIT_WLRFE_4_5_EN	BIT(2)

#define REG_GPIO_PIN_CTRL	0x0044

#define REG_LED_CFG		0x004C
#define BIT_LNAON_SEL_EN	BIT(26)
#define BIT_PAPE_SEL_EN		BIT(25)
#define BIT_DPDT_WL_SEL		BIT(24)
#define BIT_DPDT_SEL_EN		BIT(23)
#define BIT_GPIO13_14_WL_CTRL_EN	BIT(22)
#define BIT_LED2_SV		BIT(19)
#define BIT_LED2_CM		GENMASK(18, 16)
#define BIT_LED1_SV		BIT(11)
#define BIT_LED1_CM		GENMASK(10, 8)
#define BIT_LED0_SV		BIT(3)
#define BIT_LED0_CM		GENMASK(2, 0)
#define BIT_LED_MODE_SW_CTRL	0

Annotation

Implementation Notes