drivers/net/wireless/realtek/rtw88/rtw8812a.c

Source file repositories/reference/linux-study-clean/drivers/net/wireless/realtek/rtw88/rtw8812a.c

File Facts

System
Linux kernel
Corpus path
drivers/net/wireless/realtek/rtw88/rtw8812a.c
Extension
.c
Size
34030 bytes
Lines
1126
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (efuse->rfe_option == 1) {
			rtw_write32(rtwdev, REG_OFDM0_XB_TX_IQ_IMBALANCE, 0x821403e3);
			rtw_write32(rtwdev, REG_TXPITMB, 0x821403e3);
		} else {
			rtw_write32(rtwdev, REG_OFDM0_XB_TX_IQ_IMBALANCE, 0x821403f7);
			rtw_write32(rtwdev, REG_TXPITMB, 0x821403f7);
		}
	} else {
		rtw_write32(rtwdev, REG_OFDM0_XB_TX_IQ_IMBALANCE, 0x821403f1);
		rtw_write32(rtwdev, REG_TXPITMB, 0x821403f1);
	}

	if (rtwdev->hal.current_band_type == RTW_BAND_5G) {
		rtw_write32(rtwdev, REG_TSSI_TRK_SW, 0x68163e96);
		rtw_write32(rtwdev, REG_RXPITMB, 0x68163e96);
	} else {
		rtw_write32(rtwdev, REG_TSSI_TRK_SW, 0x28163e96);
		rtw_write32(rtwdev, REG_RXPITMB, 0x28163e96);

		if (efuse->rfe_option == 3) {
			if (efuse->ext_pa_2g)
				rtw_write32(rtwdev, REG_OFDM0_XB_TX_IQ_IMBALANCE,
					    0x821403e3);
			else
				rtw_write32(rtwdev, REG_OFDM0_XB_TX_IQ_IMBALANCE,
					    0x821403f7);
		}
	}

	/* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
	rtw_write32(rtwdev, REG_OFDM0_XA_TX_IQ_IMBALANCE, 0x18008c10);
	/* RX_Tone_idx[9:0], RxK_Mask[29] */
	rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x38008c10);
	rtw_write32(rtwdev, REG_INTPO_SETA, 0x00000000);
	/* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
	rtw_write32(rtwdev, REG_TXTONEB, 0x18008c10);
	/* RX_Tone_idx[9:0], RxK_Mask[29] */
	rtw_write32(rtwdev, REG_RXTONEB, 0x38008c10);
	rtw_write32(rtwdev, REG_INTPO_SETB, 0x00000000);

	cal0_retry = 0;
	cal1_retry = 0;
	while (1) {
		/* one shot */
		rtw_write32(rtwdev, REG_RFECTL_A, 0x00100000);
		rtw_write32(rtwdev, REG_RFECTL_B, 0x00100000);
		rtw_write32(rtwdev, REG_IQK_COM64, 0xfa000000);
		rtw_write32(rtwdev, REG_IQK_COM64, 0xf8000000);

		mdelay(10);

		rtw_write32(rtwdev, REG_RFECTL_A, 0x00000000);
		rtw_write32(rtwdev, REG_RFECTL_B, 0x00000000);

		for (delay_count = 0; delay_count < 20; delay_count++) {
			if (!tx0_finish)
				iqk0_ready = rtw_read32_mask(rtwdev,
							     REG_IQKA_END,
							     BIT(10));
			if (!tx1_finish)
				iqk1_ready = rtw_read32_mask(rtwdev,
							     REG_IQKB_END,
							     BIT(10));
			if (iqk0_ready && iqk1_ready)
				break;

			mdelay(1);
		}

		rtw_dbg(rtwdev, RTW_DBG_RFK, "TX delay_count = %d\n",
			delay_count);

		if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */
			/* ============TXIQK Check============== */
			tx0_fail = rtw_read32_mask(rtwdev, REG_IQKA_END, BIT(12));
			tx1_fail = rtw_read32_mask(rtwdev, REG_IQKB_END, BIT(12));

			if (!(tx0_fail || tx0_finish)) {
				rtw_write32(rtwdev, REG_RFECTL_A, 0x02000000);
				tx_x0_temp[tx0_avg] = rtw_read32_mask(rtwdev,
								      REG_IQKA_END,
								      0x07ff0000);
				rtw_write32(rtwdev, REG_RFECTL_A, 0x04000000);
				tx_y0_temp[tx0_avg] = rtw_read32_mask(rtwdev,
								      REG_IQKA_END,
								      0x07ff0000);

				rtw_dbg(rtwdev, RTW_DBG_RFK,
					"tx_x0[%d] = %x ;; tx_y0[%d] = %x\n",
					tx0_avg, tx_x0_temp[tx0_avg],

Annotation

Implementation Notes