drivers/net/wireless/realtek/rtw89/coex.c

Source file repositories/reference/linux-study-clean/drivers/net/wireless/realtek/rtw89/coex.c

File Facts

System: Linux kernel
Corpus path: drivers/net/wireless/realtek/rtw89/coex.c
Extension: .c
Size: 362000 bytes
Lines: 11907
Domain: Driver Families
Bucket: drivers/net
Inferred role: Driver Families: exported/initcall integration point
Status: integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
Allocates kernel memory; connect allocation flags and lifetime to context constraints.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

chan.h
coex.h
debug.h
fw.h
mac.h
phy.h
ps.h
reg.h

Detected Declarations

struct btc_fbtc_1slot
struct rtw89_btc_btf_tlv
struct rtw89_btc_btf_tlv_v7
struct rtw89_btc_btf_set_report_v1
struct rtw89_btc_btf_set_report_v8
struct rtw89_btc_btf_set_slot_table
struct rtw89_btc_btf_set_slot_table_v7
struct rtw89_btc_btf_set_mon_reg_v1
struct rtw89_btc_btf_set_mon_reg_v7
struct _wl_rinfo_now
struct rtw89_btc_prpt
struct btc_btinfo_lb2
struct btc_btinfo_lb3
struct btc_btinfo_hb0
struct btc_btinfo_hb1
struct btc_btinfo_hb2
struct btc_btinfo_hb3
struct rtw89_txtime_data
struct rtw89_btc_wl_sta_iter_data
enum btc_fbtc_tdma_template
enum btc_fbtc_tdma_type
enum btc_fbtc_tdma_rx_flow_ctrl
enum btc_fbtc_tdma_wlan_tx_pause
enum btc_mlme_state
enum btc_btf_set_report_en
enum btc_btf_set_cx_policy
enum btc_b2w_scoreboard
enum btc_phymap
enum btc_cx_state_map
enum btc_ant_phase
enum btc_plt
enum btc_cx_poicy_main_type
enum btc_cx_poicy_type
enum btc_wl_rfk_result
enum btc_coex_info_map_en
enum btc_w2b_scoreboard
enum btc_wl_link_mode
enum btc_wl_mrole_type
enum btc_bt_hid_type
enum btc_reset_module
enum btc_gnt_state
enum btc_ctr_path
enum btc_wlact_state
enum btc_wl_max_tx_time
enum btc_wl_max_tx_retry
enum btc_reason_and_action
enum btc_bt_a2dp_type
function chip_id_to_bt_rom_code_id

Annotated Snippet

struct btc_fbtc_1slot {
	u8 fver;
	u8 sid; /* slot id */
	struct rtw89_btc_fbtc_slot slot;
} __packed;

static const struct rtw89_btc_fbtc_tdma t_def[] = {
	[CXTD_OFF]	= { CXTDMA_OFF,    CXFLC_OFF, CXTPS_OFF, 0, 0, 0, 0, 0},
	[CXTD_OFF_B2]	= { CXTDMA_OFF,    CXFLC_OFF, CXTPS_OFF, 0, 0, 1, 0, 0},
	[CXTD_OFF_EXT]	= { CXTDMA_OFF,    CXFLC_OFF, CXTPS_OFF, 0, 0, 2, 0, 0},
	[CXTD_FIX]	= { CXTDMA_FIX,    CXFLC_OFF, CXTPS_OFF, 0, 0, 0, 0, 0},
	[CXTD_PFIX]	= { CXTDMA_FIX,  CXFLC_NULLP,  CXTPS_ON, 0, 5, 0, 0, 0},
	[CXTD_AUTO]	= { CXTDMA_AUTO,   CXFLC_OFF, CXTPS_OFF, 0, 0, 0, 0, 0},
	[CXTD_PAUTO]	= { CXTDMA_AUTO, CXFLC_NULLP,  CXTPS_ON, 0, 5, 0, 0, 0},
	[CXTD_AUTO2]	= {CXTDMA_AUTO2,   CXFLC_OFF, CXTPS_OFF, 0, 0, 0, 0, 0},
	[CXTD_PAUTO2]	= {CXTDMA_AUTO2, CXFLC_NULLP,  CXTPS_ON, 0, 5, 0, 0, 0}
};

#define __DEF_FBTC_SLOT(__dur, __cxtbl, __cxtype) \
	{ .dur = cpu_to_le16(__dur), .cxtbl = cpu_to_le32(__cxtbl), \
	  .cxtype = cpu_to_le16(__cxtype),}

static const struct rtw89_btc_fbtc_slot s_def[] = {
	[CXST_OFF]	= __DEF_FBTC_SLOT(100, 0x55555555, SLOT_MIX),
	[CXST_B2W]	= __DEF_FBTC_SLOT(5,   0xea5a5a5a, SLOT_ISO),
	[CXST_W1]	= __DEF_FBTC_SLOT(70,  0xea5a5a5a, SLOT_ISO),
	[CXST_W2]	= __DEF_FBTC_SLOT(15,  0xea5a5a5a, SLOT_ISO),
	[CXST_W2B]	= __DEF_FBTC_SLOT(15,  0xea5a5a5a, SLOT_ISO),
	[CXST_B1]	= __DEF_FBTC_SLOT(250, 0xe5555555, SLOT_MIX),
	[CXST_B2]	= __DEF_FBTC_SLOT(7,   0xea5a5a5a, SLOT_MIX),
	[CXST_B3]	= __DEF_FBTC_SLOT(5,   0xe5555555, SLOT_MIX),
	[CXST_B4]	= __DEF_FBTC_SLOT(50,  0xe5555555, SLOT_MIX),
	[CXST_LK]	= __DEF_FBTC_SLOT(20,  0xea5a5a5a, SLOT_ISO),
	[CXST_BLK]	= __DEF_FBTC_SLOT(500, 0x55555555, SLOT_MIX),
	[CXST_E2G]	= __DEF_FBTC_SLOT(5,   0xea5a5a5a, SLOT_MIX),
	[CXST_E5G]	= __DEF_FBTC_SLOT(5,   0xffffffff, SLOT_ISO),
	[CXST_EBT]	= __DEF_FBTC_SLOT(5,   0xe5555555, SLOT_MIX),
	[CXST_ENULL]	= __DEF_FBTC_SLOT(5,   0x55555555, SLOT_MIX),
	[CXST_WLK]	= __DEF_FBTC_SLOT(250, 0xea5a5a5a, SLOT_MIX),
	[CXST_W1FDD]	= __DEF_FBTC_SLOT(50,  0xffffffff, SLOT_ISO),
	[CXST_B1FDD]	= __DEF_FBTC_SLOT(50,  0xffffdfff, SLOT_ISO),
};

static const u32 cxtbl[] = {
	0xffffffff, /* 0 */
	0xaaaaaaaa, /* 1 */
	0xe5555555, /* 2 */
	0xee555555, /* 3 */
	0xd5555555, /* 4 */
	0x5a5a5a5a, /* 5 */
	0xfa5a5a5a, /* 6 */
	0xda5a5a5a, /* 7 */
	0xea5a5a5a, /* 8 */
	0x6a5a5aaa, /* 9 */
	0x6a5a6a5a, /* 10 */
	0x6a5a6aaa, /* 11 */
	0x6afa5afa, /* 12 */
	0xaaaa5aaa, /* 13 */
	0xaaffffaa, /* 14 */
	0xaa5555aa, /* 15 */
	0xfafafafa, /* 16 */
	0xffffddff, /* 17 */
	0xdaffdaff, /* 18 */
	0xfafadafa, /* 19 */
	0xea6a6a6a, /* 20 */
	0xea55556a, /* 21 */
	0xaafafafa, /* 22 */
	0xfafaaafa, /* 23 */
	0xfafffaff, /* 24 */
	0xea6a5a5a, /* 25 */
	0xfaff5aff, /* 26 */
	0xffffdfff, /* 27 */
	0xe6555555, /* 28 */
};

static const struct rtw89_btc_ver rtw89_btc_ver_defs[] = {
	/* firmware version must be in decreasing order for each chip */
	{RTL8852BT, RTW89_FW_VER_CODE(0, 29, 122, 0),
	 .fcxbtcrpt = 8, .fcxtdma = 7,    .fcxslots = 7, .fcxcysta = 7,
	 .fcxstep = 7,   .fcxnullsta = 7, .fcxmreg = 7,  .fcxgpiodbg = 7,
	 .fcxbtver = 7,  .fcxbtscan = 7,  .fcxbtafh = 7, .fcxbtdevinfo = 7,
	 .fwlrole = 7,   .frptmap = 3,    .fcxctrl = 7,  .fcxinit = 7,
	 .fwevntrptl = 1, .fwc2hfunc = 2, .drvinfo_type = 1, .info_buf = 1800,
	 .max_role_num = 6, .fcxosi = 0,  .fcxmlo = 0,   .bt_desired = 8,
	},
	{RTL8852BT, RTW89_FW_VER_CODE(0, 29, 90, 0),
	 .fcxbtcrpt = 7, .fcxtdma = 7,    .fcxslots = 7, .fcxcysta = 7,
	 .fcxstep = 7,   .fcxnullsta = 7, .fcxmreg = 7,  .fcxgpiodbg = 7,
	 .fcxbtver = 7,  .fcxbtscan = 7,  .fcxbtafh = 7, .fcxbtdevinfo = 7,
	 .fwlrole = 7,   .frptmap = 3,    .fcxctrl = 7,  .fcxinit = 7,

Annotation

Immediate include surface: `chan.h`, `coex.h`, `debug.h`, `fw.h`, `mac.h`, `phy.h`, `ps.h`, `reg.h`.
Detected declarations: `struct btc_fbtc_1slot`, `struct rtw89_btc_btf_tlv`, `struct rtw89_btc_btf_tlv_v7`, `struct rtw89_btc_btf_set_report_v1`, `struct rtw89_btc_btf_set_report_v8`, `struct rtw89_btc_btf_set_slot_table`, `struct rtw89_btc_btf_set_slot_table_v7`, `struct rtw89_btc_btf_set_mon_reg_v1`, `struct rtw89_btc_btf_set_mon_reg_v7`, `struct _wl_rinfo_now`.
Atlas domain: Driver Families / drivers/net.
Implementation status: integration implementation candidate.
Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.