drivers/net/wireless/realtek/rtw89/pci_be.c

Source file repositories/reference/linux-study-clean/drivers/net/wireless/realtek/rtw89/pci_be.c

File Facts

System
Linux kernel
Corpus path
drivers/net/wireless/realtek/rtw89/pci_be.c
Extension
.c
Size
27909 bytes
Lines
902
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (info->rxbd_mode == MAC_AX_RXBD_PKT) {
			val32_init1 = u32_replace_bits(val32_init1, PCIE_RXBD_NORM,
						       B_BE_RXQ_RXBD_MODE_MASK);
		} else if (info->rxbd_mode == MAC_AX_RXBD_SEP) {
			val32_init1 = u32_replace_bits(val32_init1, PCIE_RXBD_SEP,
						       B_BE_RXQ_RXBD_MODE_MASK);
			val32_rxapp = u32_replace_bits(val32_rxapp, 0,
						       B_BE_APPEND_LEN_MASK);
		}
	}

	val32_init1 = u32_replace_bits(val32_init1, info->tx_burst,
				       B_BE_MAX_TXDMA_MASK);
	val32_init1 = u32_replace_bits(val32_init1, info->rx_burst,
				       B_BE_MAX_RXDMA_MASK);
	val32_exp = u32_replace_bits(val32_exp, info->multi_tag_num,
				     B_BE_MAX_TAG_NUM_MASK);
	val32_init1 = u32_replace_bits(val32_init1, info->wd_dma_idle_intvl,
				       B_BE_CFG_WD_PERIOD_IDLE_MASK);
	val32_init1 = u32_replace_bits(val32_init1, info->wd_dma_act_intvl,
				       B_BE_CFG_WD_PERIOD_ACTIVE_MASK);

	rtw89_write32(rtwdev, R_BE_HAXI_INIT_CFG1, val32_init1);
	if (chip->chip_id == RTL8922A)
		rtw89_write32(rtwdev, R_BE_RX_APPEND_MODE, val32_rxapp);
	rtw89_write32(rtwdev, R_BE_HAXI_EXP_CTRL_V1, val32_exp);
}

static int rtw89_pci_rst_bdram_be(struct rtw89_dev *rtwdev)
{
	u32 val;

	rtw89_write32_set(rtwdev, R_BE_HAXI_INIT_CFG1, B_BE_SET_BDRAM_BOUND);

	return read_poll_timeout(rtw89_read32, val, !(val & B_BE_SET_BDRAM_BOUND),
				 50, 500000, false, rtwdev, R_BE_HAXI_INIT_CFG1);
}

static void rtw89_pci_debounce_be(struct rtw89_dev *rtwdev)
{
	u32 val32;

	val32 = rtw89_read32(rtwdev, R_BE_SYS_PAGE_CLK_GATED);
	val32 = u32_replace_bits(val32, 0, B_BE_PCIE_PRST_DEBUNC_PERIOD_MASK);
	val32 |= B_BE_SYM_PRST_DEBUNC_SEL;
	rtw89_write32(rtwdev, R_BE_SYS_PAGE_CLK_GATED, val32);
}

static void rtw89_pci_ldo_low_pwr_be(struct rtw89_dev *rtwdev)
{
	enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
	struct rtw89_hal *hal = &rtwdev->hal;
	u32 clr;

	rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_PSUS_OFF_CAPC_EN);
	rtw89_write32_set(rtwdev, R_BE_SYS_PAGE_CLK_GATED,
			  B_BE_SOP_OFFPOOBS_PC | B_BE_CPHY_AUXCLK_OP |
			  B_BE_CPHY_POWER_READY_CHK);
	rtw89_write32_clr(rtwdev, R_BE_SYS_SDIO_CTRL, B_BE_PCIE_FORCE_IBX_EN |
						      B_BE_PCIE_DIS_L2_RTK_PERST |
						      B_BE_PCIE_DIS_L2__CTRL_LDO_HCI);

	if (chip_id == RTL8922D && hal->cid == RTL8922D_CID7090)
		clr = B_BE_PCIE_DIS_L1_2_CTRL_HCILDO |
		      B_BE_PCIE_DIS_L1_2_CTRL_APHY_SUSB |
		      B_BE_PCIE_DIS_RTK_PRST_N_L1_2 |
		      B_BE_PCIE_DIS_L2_CTRL_APHY_SUSB;
	else
		clr = B_BE_PCIE_DIS_L1_2_CTRL_HCILDO;

	rtw89_write32_clr(rtwdev, R_BE_L1_2_CTRL_HCILDO, clr);
}

static void rtw89_pci_pcie_setting_be(struct rtw89_dev *rtwdev)
{
	const struct rtw89_chip_info *chip = rtwdev->chip;
	struct rtw89_hal *hal = &rtwdev->hal;

	rtw89_write32_set(rtwdev, R_BE_PCIE_FRZ_CLK, B_BE_PCIE_EN_AUX_CLK);
	rtw89_write32_clr(rtwdev, R_BE_PCIE_PS_CTRL, B_BE_CMAC_EXIT_L1_EN);

	if (chip->chip_id == RTL8922A && hal->cv == CHIP_CAV)
		return;

	rtw89_write32_set(rtwdev, R_BE_EFUSE_CTRL_2_V1, B_BE_R_SYM_AUTOLOAD_WITH_PMC_SEL);
	rtw89_write32_set(rtwdev, R_BE_PCIE_LAT_CTRL, B_BE_SYM_AUX_CLK_SEL);

	if (chip->chip_id != RTL8922D)
		return;

Annotation

Implementation Notes