drivers/net/wireless/realtek/rtw89/rtw8851b.c
Source file repositories/reference/linux-study-clean/drivers/net/wireless/realtek/rtw89/rtw8851b.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/wireless/realtek/rtw89/rtw8851b.c- Extension
.c- Size
- 91222 bytes
- Lines
- 2789
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
coex.hefuse.hfw.hmac.hphy.hreg.hrtw8851b.hrtw8851b_rfk.hrtw8851b_rfk_table.hrtw8851b_table.htxrx.hutil.h
Detected Declarations
struct rtw8851b_bb_gainfunction rtw8851b_pwr_on_funcfunction rtw8851b_patch_swr_pfm2pwmfunction rtw8851b_pwr_off_funcfunction rtw8851b_efuse_parsing_tssifunction _decode_efuse_gainfunction rtw8851b_efuse_parsing_gain_offsetfunction rtw8851b_read_efusefunction rtw8851b_phycap_parsing_tssifunction rtw8851b_phycap_parsing_thermal_trimfunction rtw8851b_thermal_trimfunction rtw8851b_phycap_parsing_pa_bias_trimfunction rtw8851b_pa_bias_trimfunction rtw8851b_phycap_parsing_gain_compfunction rtw8851b_phycap_parsing_adc_tdfunction rtw8851b_read_phycapfunction rtw8851b_set_bb_gpiofunction rtw8851b_set_mac_gpiofunction rtw8851b_rfe_gpiofunction rtw8851b_power_trimfunction rtw8851b_set_channel_macfunction rtw8851b_ctrl_sco_cckfunction rtw8851b_sco_mappingfunction rtw8851b_set_gain_errorfunction rtw8851b_set_gain_offsetfunction rtw8851b_set_rxsc_rpl_compfunction rtw8851b_ctrl_chfunction rtw8851b_bw_settingfunction rtw8851b_ctrl_bwfunction rtw8851b_ctrl_cck_enfunction rtw8851b_spur_freqfunction rtw8851b_set_csi_tone_idxfunction rtw8851b_set_nbi_tone_idxfunction rtw8851b_set_cfrfunction rtw8851b_5m_maskfunction rtw8851b_bb_reset_allfunction rtw8851b_bb_reset_enfunction rtw8851b_bb_resetfunction rtw8851b_bb_gpio_trswfunction rtw8851b_bb_gpio_initfunction rtw8851b_bb_macid_ctrl_initfunction rtw8851b_bb_sethwfunction rtw8851b_set_channel_bbfunction rtw8851b_set_channelfunction rtw8851b_tssi_cont_enfunction rtw8851b_tssi_cont_en_phyidxfunction rtw8851b_adc_enfunction rtw8851b_set_channel_help
Annotated Snippet
struct rtw8851b_bb_gain {
u32 gain_g[BB_PATH_NUM_8851B];
u32 gain_a[BB_PATH_NUM_8851B];
u32 gain_mask;
};
static const struct rtw8851b_bb_gain bb_gain_lna[LNA_GAIN_NUM] = {
{ .gain_g = {0x4678}, .gain_a = {0x45DC},
.gain_mask = 0x00ff0000 },
{ .gain_g = {0x4678}, .gain_a = {0x45DC},
.gain_mask = 0xff000000 },
{ .gain_g = {0x467C}, .gain_a = {0x4660},
.gain_mask = 0x000000ff },
{ .gain_g = {0x467C}, .gain_a = {0x4660},
.gain_mask = 0x0000ff00 },
{ .gain_g = {0x467C}, .gain_a = {0x4660},
.gain_mask = 0x00ff0000 },
{ .gain_g = {0x467C}, .gain_a = {0x4660},
.gain_mask = 0xff000000 },
{ .gain_g = {0x4680}, .gain_a = {0x4664},
.gain_mask = 0x000000ff },
};
static const struct rtw8851b_bb_gain bb_gain_tia[TIA_GAIN_NUM] = {
{ .gain_g = {0x4680}, .gain_a = {0x4664},
.gain_mask = 0x00ff0000 },
{ .gain_g = {0x4680}, .gain_a = {0x4664},
.gain_mask = 0xff000000 },
};
static void rtw8851b_set_gain_error(struct rtw89_dev *rtwdev,
enum rtw89_subband subband,
enum rtw89_rf_path path)
{
const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
u8 gain_band = rtw89_subband_to_bb_gain_band(subband);
s32 val;
u32 reg;
u32 mask;
int i;
for (i = 0; i < LNA_GAIN_NUM; i++) {
if (subband == RTW89_CH_2G)
reg = bb_gain_lna[i].gain_g[path];
else
reg = bb_gain_lna[i].gain_a[path];
mask = bb_gain_lna[i].gain_mask;
val = gain->lna_gain[gain_band][path][i];
rtw89_phy_write32_mask(rtwdev, reg, mask, val);
}
for (i = 0; i < TIA_GAIN_NUM; i++) {
if (subband == RTW89_CH_2G)
reg = bb_gain_tia[i].gain_g[path];
else
reg = bb_gain_tia[i].gain_a[path];
mask = bb_gain_tia[i].gain_mask;
val = gain->tia_gain[gain_band][path][i];
rtw89_phy_write32_mask(rtwdev, reg, mask, val);
}
}
static void rtw8851b_set_gain_offset(struct rtw89_dev *rtwdev,
enum rtw89_subband subband,
enum rtw89_phy_idx phy_idx)
{
static const u32 rssi_ofst_addr[] = {R_PATH0_G_TIA1_LNA6_OP1DB_V1};
static const u32 gain_err_addr[] = {R_P0_AGC_RSVD};
struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain;
enum rtw89_gain_offset gain_ofdm_band;
s32 offset_ofdm, offset_cck;
s32 offset_a;
s32 tmp;
u8 path;
if (!efuse_gain->comp_valid)
goto next;
for (path = RF_PATH_A; path < BB_PATH_NUM_8851B; path++) {
tmp = efuse_gain->comp[path][subband];
tmp = clamp_t(s32, tmp << 2, S8_MIN, S8_MAX);
rtw89_phy_write32_mask(rtwdev, gain_err_addr[path], MASKBYTE0, tmp);
}
next:
if (!efuse_gain->offset_valid)
return;
Annotation
- Immediate include surface: `coex.h`, `efuse.h`, `fw.h`, `mac.h`, `phy.h`, `reg.h`, `rtw8851b.h`, `rtw8851b_rfk.h`.
- Detected declarations: `struct rtw8851b_bb_gain`, `function rtw8851b_pwr_on_func`, `function rtw8851b_patch_swr_pfm2pwm`, `function rtw8851b_pwr_off_func`, `function rtw8851b_efuse_parsing_tssi`, `function _decode_efuse_gain`, `function rtw8851b_efuse_parsing_gain_offset`, `function rtw8851b_read_efuse`, `function rtw8851b_phycap_parsing_tssi`, `function rtw8851b_phycap_parsing_thermal_trim`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: integration implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.