drivers/net/wireless/realtek/rtw89/rtw8852bt.c

Source file repositories/reference/linux-study-clean/drivers/net/wireless/realtek/rtw89/rtw8852bt.c

File Facts

System
Linux kernel
Corpus path
drivers/net/wireless/realtek/rtw89/rtw8852bt.c
Extension
.c
Size
33574 bytes
Lines
960
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (md->md_v7.rfe_type == 0) {
			rtwdev->btc.dm.error.map.rfe_type0 = true;
			return;
		}

		md->md_v7.ant.num = (md->md_v7.rfe_type % 2) ? 2 : 3;
		md->md_v7.ant.stream_cnt = 2;
		md->md_v7.wa_type |= BTC_WA_INIT_SCAN;

		if (md->md_v7.ant.num == 2) {
			md->md_v7.ant.type = BTC_ANT_SHARED;
			md->md_v7.bt_pos = BTC_BT_BTG;
			md->md_v7.wa_type |= BTC_WA_HFP_LAG;
		} else {
			md->md_v7.ant.type = BTC_ANT_DEDICATED;
			md->md_v7.bt_pos = BTC_BT_ALONE;
		}
	} else {
		return;
	}
}

static void
rtw8852bt_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
{
	u16 ctrl_all_time = u32_get_bits(txpwr_val, GENMASK(15, 0));
	u16 ctrl_gnt_bt = u32_get_bits(txpwr_val, GENMASK(31, 16));

	switch (ctrl_all_time) {
	case 0xffff:
		rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_AX_PWR_RATE_CTRL,
					     B_AX_FORCE_PWR_BY_RATE_EN, 0x0);
		rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_AX_PWR_RATE_CTRL,
					     B_AX_FORCE_PWR_BY_RATE_VALUE_MASK, 0x0);
		break;
	default:
		rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_AX_PWR_RATE_CTRL,
					     B_AX_FORCE_PWR_BY_RATE_VALUE_MASK,
					     ctrl_all_time);
		rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_AX_PWR_RATE_CTRL,
					     B_AX_FORCE_PWR_BY_RATE_EN, 0x1);
		break;
	}

	switch (ctrl_gnt_bt) {
	case 0xffff:
		rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_AX_PWR_COEXT_CTRL,
					     B_AX_TXAGC_BT_EN, 0x0);
		rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_AX_PWR_COEXT_CTRL,
					     B_AX_TXAGC_BT_MASK, 0x0);
		break;
	default:
		rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_AX_PWR_COEXT_CTRL,
					     B_AX_TXAGC_BT_MASK, ctrl_gnt_bt);
		rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_AX_PWR_COEXT_CTRL,
					     B_AX_TXAGC_BT_EN, 0x1);
		break;
	}
}

static const struct rtw89_chip_ops rtw8852bt_chip_ops = {
	.enable_bb_rf		= rtw8852bx_mac_enable_bb_rf,
	.disable_bb_rf		= rtw8852bx_mac_disable_bb_rf,
	.bb_preinit		= NULL,
	.bb_postinit		= NULL,
	.bb_reset		= rtw8852bt_bb_reset,
	.bb_sethw		= rtw8852bx_bb_sethw,
	.read_rf		= rtw89_phy_read_rf_v1,
	.write_rf		= rtw89_phy_write_rf_v1,
	.set_channel		= rtw8852bt_set_channel,
	.set_channel_help	= rtw8852bt_set_channel_help,
	.read_efuse		= rtw8852bx_read_efuse,
	.read_phycap		= rtw8852bx_read_phycap,
	.fem_setup		= NULL,
	.data_setup		= NULL,
	.rfe_gpio		= NULL,
	.rfk_hw_init		= NULL,
	.rfk_init		= rtw8852bt_rfk_init,
	.rfk_init_late		= NULL,
	.rfk_channel		= rtw8852bt_rfk_channel,
	.rfk_band_changed	= rtw8852bt_rfk_band_changed,
	.rfk_scan		= rtw8852bt_rfk_scan,
	.rfk_track		= rtw8852bt_rfk_track,
	.power_trim		= rtw8852bx_power_trim,
	.set_txpwr		= rtw8852bx_set_txpwr,
	.set_txpwr_ctrl		= rtw8852bx_set_txpwr_ctrl,
	.init_txpwr_unit	= rtw8852bx_init_txpwr_unit,
	.get_thermal		= rtw8852bx_get_thermal,
	.chan_to_rf18_val	= NULL,
	.ctrl_btg_bt_rx		= rtw8852bx_ctrl_btg_bt_rx,

Annotation

Implementation Notes