drivers/net/wireless/zydas/zd1211rw/zd_rf_rf2959.c

Source file repositories/reference/linux-study-clean/drivers/net/wireless/zydas/zd1211rw/zd_rf_rf2959.c

File Facts

System
Linux kernel
Corpus path
drivers/net/wireless/zydas/zd1211rw/zd_rf_rf2959.c
Extension
.c
Size
8221 bytes
Lines
270
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-or-later
/* ZD1211 USB-WLAN driver for Linux
 *
 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
 */

#include <linux/kernel.h>

#include "zd_rf.h"
#include "zd_usb.h"
#include "zd_chip.h"

static const u32 rf2959_table[][2] = {
	RF_CHANNEL( 1) = { 0x181979, 0x1e6666 },
	RF_CHANNEL( 2) = { 0x181989, 0x1e6666 },
	RF_CHANNEL( 3) = { 0x181999, 0x1e6666 },
	RF_CHANNEL( 4) = { 0x1819a9, 0x1e6666 },
	RF_CHANNEL( 5) = { 0x1819b9, 0x1e6666 },
	RF_CHANNEL( 6) = { 0x1819c9, 0x1e6666 },
	RF_CHANNEL( 7) = { 0x1819d9, 0x1e6666 },
	RF_CHANNEL( 8) = { 0x1819e9, 0x1e6666 },
	RF_CHANNEL( 9) = { 0x1819f9, 0x1e6666 },
	RF_CHANNEL(10) = { 0x181a09, 0x1e6666 },
	RF_CHANNEL(11) = { 0x181a19, 0x1e6666 },
	RF_CHANNEL(12) = { 0x181a29, 0x1e6666 },
	RF_CHANNEL(13) = { 0x181a39, 0x1e6666 },
	RF_CHANNEL(14) = { 0x181a60, 0x1c0000 },
};

#if 0
static int bits(u32 rw, int from, int to)
{
	rw &= ~(0xffffffffU << (to+1));
	rw >>= from;
	return rw;
}

static int bit(u32 rw, int bit)
{
	return bits(rw, bit, bit);
}

static void dump_regwrite(u32 rw)
{
	int reg = bits(rw, 18, 22);
	int rw_flag = bits(rw, 23, 23);
	PDEBUG("rf2959 %#010x reg %d rw %d", rw, reg, rw_flag);

	switch (reg) {
	case 0:
		PDEBUG("reg0 CFG1 ref_sel %d hibernate %d rf_vco_reg_en %d"
		       " if_vco_reg_en %d if_vga_en %d",
		       bits(rw, 14, 15), bit(rw, 3), bit(rw, 2), bit(rw, 1),
		       bit(rw, 0));
		break;
	case 1:
		PDEBUG("reg1 IFPLL1 pll_en1 %d kv_en1 %d vtc_en1 %d lpf1 %d"
		       " cpl1 %d pdp1 %d autocal_en1 %d ld_en1 %d ifloopr %d"
		       " ifloopc %d dac1 %d",
		       bit(rw, 17), bit(rw, 16), bit(rw, 15), bit(rw, 14),
		       bit(rw, 13), bit(rw, 12), bit(rw, 11), bit(rw, 10),
		       bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0, 3));
		break;
	case 2:
		PDEBUG("reg2 IFPLL2 n1 %d num1 %d",
		       bits(rw, 6, 17), bits(rw, 0, 5));
		break;
	case 3:
		PDEBUG("reg3 IFPLL3 num %d", bits(rw, 0, 17));
		break;
	case 4:
		PDEBUG("reg4 IFPLL4 dn1 %#04x ct_def1 %d kv_def1 %d",
		       bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3));
		break;
	case 5:
		PDEBUG("reg5 RFPLL1 pll_en %d kv_en %d vtc_en %d lpf %d cpl %d"
		       " pdp %d autocal_en %d ld_en %d rfloopr %d rfloopc %d"
		       " dac %d",
		       bit(rw, 17), bit(rw, 16), bit(rw, 15), bit(rw, 14),
		       bit(rw, 13), bit(rw, 12), bit(rw, 11), bit(rw, 10),
		       bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0,3));
		break;
	case 6:
		PDEBUG("reg6 RFPLL2 n %d num %d",
		       bits(rw, 6, 17), bits(rw, 0, 5));
		break;
	case 7:
		PDEBUG("reg7 RFPLL3 num2 %d", bits(rw, 0, 17));
		break;

Annotation

Implementation Notes