drivers/net/wwan/t7xx/t7xx_cldma.c

Source file repositories/reference/linux-study-clean/drivers/net/wwan/t7xx/t7xx_cldma.c

File Facts

System
Linux kernel
Corpus path
drivers/net/wwan/t7xx/t7xx_cldma.c
Extension
.c
Size
8488 bytes
Lines
282
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2021, MediaTek Inc.
 * Copyright (c) 2021-2022, Intel Corporation.
 *
 * Authors:
 *  Haijun Liu <haijun.liu@mediatek.com>
 *  Moises Veleta <moises.veleta@intel.com>
 *  Ricardo Martinez <ricardo.martinez@linux.intel.com>
 *
 * Contributors:
 *  Amir Hanania <amir.hanania@intel.com>
 *  Andy Shevchenko <andriy.shevchenko@linux.intel.com>
 *  Eliot Lee <eliot.lee@intel.com>
 *  Sreehari Kancharla <sreehari.kancharla@intel.com>
 */

#include <linux/bits.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/types.h>

#include "t7xx_cldma.h"

#define ADDR_SIZE	8

void t7xx_cldma_clear_ip_busy(struct t7xx_cldma_hw *hw_info)
{
	u32 val;

	val = ioread32(hw_info->ap_pdn_base + REG_CLDMA_IP_BUSY);
	val |= IP_BUSY_WAKEUP;
	iowrite32(val, hw_info->ap_pdn_base + REG_CLDMA_IP_BUSY);
}

/**
 * t7xx_cldma_hw_restore() - Restore CLDMA HW registers.
 * @hw_info: Pointer to struct t7xx_cldma_hw.
 *
 * Restore HW after resume. Writes uplink configuration for CLDMA HW.
 */
void t7xx_cldma_hw_restore(struct t7xx_cldma_hw *hw_info)
{
	u32 ul_cfg;

	ul_cfg = ioread32(hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);
	ul_cfg &= ~UL_CFG_BIT_MODE_MASK;

	if (hw_info->hw_mode == MODE_BIT_64)
		ul_cfg |= UL_CFG_BIT_MODE_64;
	else if (hw_info->hw_mode == MODE_BIT_40)
		ul_cfg |= UL_CFG_BIT_MODE_40;
	else if (hw_info->hw_mode == MODE_BIT_36)
		ul_cfg |= UL_CFG_BIT_MODE_36;

	iowrite32(ul_cfg, hw_info->ap_pdn_base + REG_CLDMA_UL_CFG);
	/* Disable TX and RX invalid address check */
	iowrite32(UL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_UL_MEM);
	iowrite32(DL_MEM_CHECK_DIS, hw_info->ap_pdn_base + REG_CLDMA_DL_MEM);
}

void t7xx_cldma_hw_start_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno,
			       enum mtk_txrx tx_rx)
{
	void __iomem *reg;
	u32 val;

	reg = tx_rx == MTK_RX ? hw_info->ap_pdn_base + REG_CLDMA_DL_START_CMD :
				hw_info->ap_pdn_base + REG_CLDMA_UL_START_CMD;
	val = qno == CLDMA_ALL_Q ? CLDMA_ALL_Q : BIT(qno);
	iowrite32(val, reg);
}

void t7xx_cldma_hw_start(struct t7xx_cldma_hw *hw_info)
{
	/* Enable the TX & RX interrupts */
	iowrite32(TXRX_STATUS_BITMASK, hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0);
	iowrite32(TXRX_STATUS_BITMASK, hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0);
	/* Enable the empty queue interrupt */
	iowrite32(EMPTY_STATUS_BITMASK, hw_info->ap_pdn_base + REG_CLDMA_L2TIMCR0);
	iowrite32(EMPTY_STATUS_BITMASK, hw_info->ap_ao_base + REG_CLDMA_L2RIMCR0);
}

void t7xx_cldma_hw_reset(void __iomem *ao_base)
{
	u32 val;

	val = ioread32(ao_base + REG_INFRA_RST2_SET);
	val |= RST2_PMIC_SW_RST_SET;

Annotation

Implementation Notes