drivers/net/wwan/t7xx/t7xx_dpmaif.h

Source file repositories/reference/linux-study-clean/drivers/net/wwan/t7xx/t7xx_dpmaif.h

File Facts

System
Linux kernel
Corpus path
drivers/net/wwan/t7xx/t7xx_dpmaif.h
Extension
.h
Size
6351 bytes
Lines
180
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dpmaif_isr_en_mask {
	unsigned int			ap_ul_l2intr_en_msk;
	unsigned int			ap_dl_l2intr_en_msk;
	unsigned int			ap_udl_ip_busy_en_msk;
	unsigned int			ap_dl_l2intr_err_en_msk;
};

struct dpmaif_ul {
	bool				que_started;
	unsigned char			reserved[3];
	dma_addr_t			drb_base;
	unsigned int			drb_size_cnt;
};

struct dpmaif_dl {
	bool				que_started;
	unsigned char			reserved[3];
	dma_addr_t			pit_base;
	unsigned int			pit_size_cnt;
	dma_addr_t			bat_base;
	unsigned int			bat_size_cnt;
	dma_addr_t			frg_base;
	unsigned int			frg_size_cnt;
	unsigned int			pit_seq;
};

struct dpmaif_hw_info {
	struct device			*dev;
	void __iomem			*pcie_base;
	struct dpmaif_dl		dl_que[DPMAIF_RXQ_NUM];
	struct dpmaif_ul		ul_que[DPMAIF_TXQ_NUM];
	struct dpmaif_isr_en_mask	isr_en_mask;
};

/* DPMAIF HW Initialization parameter structure */
struct dpmaif_hw_params {
	/* UL part */
	dma_addr_t			drb_base_addr[DPMAIF_TXQ_NUM];
	unsigned int			drb_size_cnt[DPMAIF_TXQ_NUM];
	/* DL part */
	dma_addr_t			pkt_bat_base_addr[DPMAIF_RXQ_NUM];
	unsigned int			pkt_bat_size_cnt[DPMAIF_RXQ_NUM];
	dma_addr_t			frg_bat_base_addr[DPMAIF_RXQ_NUM];
	unsigned int			frg_bat_size_cnt[DPMAIF_RXQ_NUM];
	dma_addr_t			pit_base_addr[DPMAIF_RXQ_NUM];
	unsigned int			pit_size_cnt[DPMAIF_RXQ_NUM];
};

enum dpmaif_hw_intr_type {
	DPF_INTR_INVALID_MIN,
	DPF_INTR_UL_DONE,
	DPF_INTR_UL_DRB_EMPTY,
	DPF_INTR_UL_MD_NOTREADY,
	DPF_INTR_UL_MD_PWR_NOTREADY,
	DPF_INTR_UL_LEN_ERR,
	DPF_INTR_DL_DONE,
	DPF_INTR_DL_SKB_LEN_ERR,
	DPF_INTR_DL_BATCNT_LEN_ERR,
	DPF_INTR_DL_PITCNT_LEN_ERR,
	DPF_INTR_DL_PKT_EMPTY_SET,
	DPF_INTR_DL_FRG_EMPTY_SET,
	DPF_INTR_DL_MTU_ERR,
	DPF_INTR_DL_FRGCNT_LEN_ERR,
	DPF_INTR_DL_Q0_PITCNT_LEN_ERR,
	DPF_INTR_DL_Q1_PITCNT_LEN_ERR,
	DPF_INTR_DL_HPC_ENT_TYPE_ERR,
	DPF_INTR_DL_Q0_DONE,
	DPF_INTR_DL_Q1_DONE,
	DPF_INTR_INVALID_MAX
};

#define DPF_RX_QNO0			0
#define DPF_RX_QNO1			1
#define DPF_RX_QNO_DFT			DPF_RX_QNO0

struct dpmaif_hw_intr_st_para {
	unsigned int intr_cnt;
	enum dpmaif_hw_intr_type intr_types[DPF_INTR_INVALID_MAX - 1];
	unsigned int intr_queues[DPF_INTR_INVALID_MAX - 1];
};

#define DPMAIF_HW_BAT_REMAIN		64
#define DPMAIF_HW_BAT_PKTBUF		(128 * 28)
#define DPMAIF_HW_FRG_PKTBUF		128
#define DPMAIF_HW_BAT_RSVLEN		64
#define DPMAIF_HW_PKT_BIDCNT		1
#define DPMAIF_HW_MTU_SIZE		(3 * 1024 + 8)
#define DPMAIF_HW_CHK_BAT_NUM		62
#define DPMAIF_HW_CHK_FRG_NUM		3
#define DPMAIF_HW_CHK_PIT_NUM		(2 * DPMAIF_HW_CHK_BAT_NUM)

Annotation

Implementation Notes