drivers/net/wwan/t7xx/t7xx_pcie_mac.c

Source file repositories/reference/linux-study-clean/drivers/net/wwan/t7xx/t7xx_pcie_mac.c

File Facts

System
Linux kernel
Corpus path
drivers/net/wwan/t7xx/t7xx_pcie_mac.c
Extension
.c
Size
6982 bytes
Lines
263
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct t7xx_atr_config {
	u64			src_addr;
	u64			trsl_addr;
	u64			size;
	u32			port;
	u32			table;
	enum t7xx_atr_dst_port	trsl_id;
	u32			transparent;
};

static void t7xx_pcie_mac_atr_tables_dis(void __iomem *pbase, enum t7xx_atr_src_port port)
{
	void __iomem *reg;
	int i, offset;

	for (i = 0; i < ATR_TABLE_NUM_PER_ATR; i++) {
		offset = ATR_PORT_OFFSET * port + ATR_TABLE_OFFSET * i;
		reg = pbase + ATR_PCIE_WIN0_T0_ATR_PARAM_SRC_ADDR + offset;
		iowrite64_lo_hi(0, reg);
	}
}

static int t7xx_pcie_mac_atr_cfg(struct t7xx_pci_dev *t7xx_dev, struct t7xx_atr_config *cfg)
{
	struct device *dev = &t7xx_dev->pdev->dev;
	void __iomem *pbase = IREG_BASE(t7xx_dev);
	int atr_size, pos, offset;
	void __iomem *reg;
	u64 value;

	if (cfg->transparent) {
		/* No address conversion is performed */
		atr_size = ATR_TRANSPARENT_SIZE;
	} else {
		if (cfg->src_addr & (cfg->size - 1)) {
			dev_err(dev, "Source address is not aligned to size\n");
			return -EINVAL;
		}

		if (cfg->trsl_addr & (cfg->size - 1)) {
			dev_err(dev, "Translation address %llx is not aligned to size %llx\n",
				cfg->trsl_addr, cfg->size - 1);
			return -EINVAL;
		}

		pos = __ffs64(cfg->size);

		/* HW calculates the address translation space as 2^(atr_size + 1) */
		atr_size = pos - 1;
	}

	offset = ATR_PORT_OFFSET * cfg->port + ATR_TABLE_OFFSET * cfg->table;

	reg = pbase + ATR_PCIE_WIN0_T0_TRSL_ADDR + offset;
	value = cfg->trsl_addr & ATR_PCIE_WIN0_ADDR_ALGMT;
	iowrite64_lo_hi(value, reg);

	reg = pbase + ATR_PCIE_WIN0_T0_TRSL_PARAM + offset;
	iowrite32(cfg->trsl_id, reg);

	reg = pbase + ATR_PCIE_WIN0_T0_ATR_PARAM_SRC_ADDR + offset;
	value = (cfg->src_addr & ATR_PCIE_WIN0_ADDR_ALGMT) | (atr_size << 1) | BIT(0);
	iowrite64_lo_hi(value, reg);

	/* Ensure ATR is set */
	ioread64_lo_hi(reg);
	return 0;
}

/**
 * t7xx_pcie_mac_atr_init() - Initialize address translation.
 * @t7xx_dev: MTK device.
 *
 * Setup ATR for ports & device.
 */
void t7xx_pcie_mac_atr_init(struct t7xx_pci_dev *t7xx_dev)
{
	struct t7xx_atr_config cfg;
	u32 i;

	/* Disable for all ports */
	for (i = ATR_SRC_PCI_WIN0; i <= ATR_SRC_AXIS_3; i++)
		t7xx_pcie_mac_atr_tables_dis(IREG_BASE(t7xx_dev), i);

	memset(&cfg, 0, sizeof(cfg));
	/* Config ATR for RC to access device's register */
	cfg.src_addr = pci_resource_start(t7xx_dev->pdev, T7XX_PCIE_REG_BAR);
	cfg.size = T7XX_PCIE_REG_SIZE_CHIP;
	cfg.trsl_addr = T7XX_PCIE_REG_TRSL_ADDR_CHIP;
	cfg.port = T7XX_PCIE_REG_PORT;

Annotation

Implementation Notes