drivers/ntb/hw/intel/ntb_hw_gen3.c
Source file repositories/reference/linux-study-clean/drivers/ntb/hw/intel/ntb_hw_gen3.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/ntb/hw/intel/ntb_hw_gen3.c- Extension
.c- Size
- 18169 bytes
- Lines
- 631
- Domain
- Driver Families
- Bucket
- drivers/ntb
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/debugfs.hlinux/delay.hlinux/init.hlinux/interrupt.hlinux/module.hlinux/pci.hlinux/random.hlinux/slab.hlinux/ntb.hntb_hw_intel.hntb_hw_gen1.hntb_hw_gen3.h
Detected Declarations
function gen3_poll_linkfunction gen3_init_isrfunction gen3_setup_b2b_mwfunction gen3_init_ntbfunction gen3_init_devfunction ndev_ntb3_debugfs_readfunction intel_ntb3_link_enablefunction intel_ntb3_mw_set_transfunction intel_ntb3_peer_db_addrfunction intel_ntb3_peer_db_setfunction intel_ntb3_db_readfunction intel_ntb3_db_clear
Annotated Snippet
if (ndev->ntb.topo == NTB_TOPO_B2B_USD) {
rc = gen3_setup_b2b_mw(ndev,
&xeon_b2b_dsd_addr,
&xeon_b2b_usd_addr);
} else {
rc = gen3_setup_b2b_mw(ndev,
&xeon_b2b_usd_addr,
&xeon_b2b_dsd_addr);
}
if (rc)
return rc;
/* Enable Bus Master and Memory Space on the secondary side */
iowrite16(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
ndev->self_mmio + GEN3_SPCICMD_OFFSET);
break;
default:
return -EINVAL;
}
ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1;
/* Make sure we are not using DB's used for link status */
if (ndev->hwerr_flags & NTB_HWERR_MSIX_VECTOR32_BAD)
ndev->db_valid_mask &= ~ndev->db_link_mask;
ndev->reg->db_iowrite(ndev->db_valid_mask,
ndev->self_mmio +
ndev->self_reg->db_mask);
return 0;
}
int gen3_init_dev(struct intel_ntb_dev *ndev)
{
struct pci_dev *pdev;
u8 ppd;
int rc;
pdev = ndev->ntb.pdev;
ndev->reg = &gen3_reg;
rc = pci_read_config_byte(pdev, XEON_PPD_OFFSET, &ppd);
if (rc)
return -EIO;
ndev->ntb.topo = xeon_ppd_topo(ndev, ppd);
dev_dbg(&pdev->dev, "ppd %#x topo %s\n", ppd,
ntb_topo_string(ndev->ntb.topo));
if (ndev->ntb.topo == NTB_TOPO_NONE)
return -EINVAL;
ndev->hwerr_flags |= NTB_HWERR_MSIX_VECTOR32_BAD;
rc = gen3_init_ntb(ndev);
if (rc)
return rc;
return gen3_init_isr(ndev);
}
ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf,
size_t count, loff_t *offp)
{
struct intel_ntb_dev *ndev;
void __iomem *mmio;
char *buf;
size_t buf_size;
ssize_t ret, off;
union { u64 v64; u32 v32; u16 v16; } u;
ndev = filp->private_data;
mmio = ndev->self_mmio;
buf_size = min(count, 0x800ul);
buf = kmalloc(buf_size, GFP_KERNEL);
if (!buf)
return -ENOMEM;
off = 0;
off += scnprintf(buf + off, buf_size - off,
"NTB Device Information:\n");
off += scnprintf(buf + off, buf_size - off,
"Connection Topology -\t%s\n",
Annotation
- Immediate include surface: `linux/debugfs.h`, `linux/delay.h`, `linux/init.h`, `linux/interrupt.h`, `linux/module.h`, `linux/pci.h`, `linux/random.h`, `linux/slab.h`.
- Detected declarations: `function gen3_poll_link`, `function gen3_init_isr`, `function gen3_setup_b2b_mw`, `function gen3_init_ntb`, `function gen3_init_dev`, `function ndev_ntb3_debugfs_read`, `function intel_ntb3_link_enable`, `function intel_ntb3_mw_set_trans`, `function intel_ntb3_peer_db_addr`, `function intel_ntb3_peer_db_set`.
- Atlas domain: Driver Families / drivers/ntb.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.