drivers/nvme/host/pci.c
Source file repositories/reference/linux-study-clean/drivers/nvme/host/pci.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/nvme/host/pci.c- Extension
.c- Size
- 119353 bytes
- Lines
- 4331
- Domain
- Representative Device Path
- Bucket
- PCIe NVMe Storage Path
- Inferred role
- Representative Device Path: operation-table or driver-model contract
- Status
- pattern implementation candidate
Why This File Exists
Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.
- Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.
- Defines an operation table; this is where Linux turns generic core objects into subsystem-specific behavior.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/acpi.hlinux/async.hlinux/blkdev.hlinux/blk-mq-dma.hlinux/blk-integrity.hlinux/dmi.hlinux/init.hlinux/interrupt.hlinux/io.hlinux/kstrtox.hlinux/memremap.hlinux/mm.hlinux/module.hlinux/mutex.hlinux/nodemask.hlinux/once.hlinux/pci.hlinux/suspend.hlinux/t10-pi.hlinux/types.hlinux/io-64-nonatomic-lo-hi.hlinux/io-64-nonatomic-hi-lo.hlinux/sed-opal.htrace.hnvme.h
Detected Declarations
struct quirk_entrystruct nvme_devstruct nvme_queuestruct nvme_descriptor_poolsstruct nvme_devstruct nvme_queuestruct nvme_dma_vecstruct nvme_iodenum nvme_iod_flagsenum nvme_use_sglfunction nvme_parse_quirk_namesfunction nvme_parse_quirk_entryfunction quirks_param_setfunction io_queue_count_setfunction io_queue_depth_setfunction sq_idxfunction cq_idxfunction nvme_dbbuf_sizefunction nvme_dbbuf_dma_allocfunction nvme_dbbuf_dma_freefunction nvme_dbbuf_initfunction nvme_dbbuf_freefunction nvme_dbbuf_setfunction nvme_dbbuf_need_eventfunction nvme_dbbuf_update_and_check_eventfunction nvme_setup_descriptor_poolsfunction nvme_release_descriptor_poolsfunction nvme_init_hctx_commonfunction nvme_admin_init_hctxfunction nvme_init_hctxfunction nvme_pci_init_requestfunction queue_irq_offsetfunction nvme_pci_map_queuesfunction nvme_write_sq_dbfunction nvme_sq_copy_cmdfunction nvme_commit_rqsfunction nvme_pci_metadata_use_sglsfunction nvme_pci_use_sglsfunction nvme_pci_avg_seg_sizefunction nvme_pci_cmd_use_meta_sglfunction nvme_pci_cmd_use_sglfunction nvme_pci_first_desc_dma_addrfunction nvme_free_descriptorsfunction nvme_free_prpsfunction nvme_free_sglsfunction nvme_unmap_metadatafunction nvme_unmap_datafunction nvme_pci_prp_save_mapping
Annotated Snippet
static const struct blk_mq_ops nvme_mq_admin_ops = {
.queue_rq = nvme_queue_rq,
.complete = nvme_pci_complete_rq,
.commit_rqs = nvme_commit_rqs,
.init_hctx = nvme_admin_init_hctx,
.init_request = nvme_pci_init_request,
.timeout = nvme_timeout,
};
static const struct blk_mq_ops nvme_mq_ops = {
.queue_rq = nvme_queue_rq,
.queue_rqs = nvme_queue_rqs,
.complete = nvme_pci_complete_rq,
.commit_rqs = nvme_commit_rqs,
.init_hctx = nvme_init_hctx,
.init_request = nvme_pci_init_request,
.map_queues = nvme_pci_map_queues,
.timeout = nvme_timeout,
.poll = nvme_poll,
};
static void nvme_dev_remove_admin(struct nvme_dev *dev)
{
if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
/*
* If the controller was reset during removal, it's possible
* user requests may be waiting on a stopped queue. Start the
* queue to flush these to completion.
*/
nvme_unquiesce_admin_queue(&dev->ctrl);
nvme_remove_admin_tag_set(&dev->ctrl);
}
}
static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
{
return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
}
static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
{
struct pci_dev *pdev = to_pci_dev(dev->dev);
if (size <= dev->bar_mapped_size)
return 0;
if (size > pci_resource_len(pdev, 0))
return -ENOMEM;
if (dev->bar)
iounmap(dev->bar);
dev->bar = ioremap(pci_resource_start(pdev, 0), size);
if (!dev->bar) {
dev->bar_mapped_size = 0;
return -ENOMEM;
}
dev->bar_mapped_size = size;
dev->dbs = dev->bar + NVME_REG_DBS;
return 0;
}
static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
{
int result;
u32 aqa;
struct nvme_queue *nvmeq;
result = nvme_remap_bar(dev, db_bar_size(dev, 0));
if (result < 0)
return result;
dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
if (dev->subsystem &&
(readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
/*
* If the device has been passed off to us in an enabled state, just
* clear the enabled bit. The spec says we should set the 'shutdown
* notification bits', but doing so may cause the device to complete
* commands to the admin queue ... and we don't know what memory that
* might be pointing at!
*/
result = nvme_disable_ctrl(&dev->ctrl, false);
if (result < 0) {
struct pci_dev *pdev = to_pci_dev(dev->dev);
/*
* The NVMe Controller Reset method did not get an expected
Annotation
- Immediate include surface: `linux/acpi.h`, `linux/async.h`, `linux/blkdev.h`, `linux/blk-mq-dma.h`, `linux/blk-integrity.h`, `linux/dmi.h`, `linux/init.h`, `linux/interrupt.h`.
- Detected declarations: `struct quirk_entry`, `struct nvme_dev`, `struct nvme_queue`, `struct nvme_descriptor_pools`, `struct nvme_dev`, `struct nvme_queue`, `struct nvme_dma_vec`, `struct nvme_iod`, `enum nvme_iod_flags`, `enum nvme_use_sgl`.
- Atlas domain: Representative Device Path / PCIe NVMe Storage Path.
- Implementation status: pattern implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.