drivers/of/unittest-data/overlay_bad_add_dup_node.dtso
Source file repositories/reference/linux-study-clean/drivers/of/unittest-data/overlay_bad_add_dup_node.dtso
File Facts
- System
- Linux kernel
- Corpus path
drivers/of/unittest-data/overlay_bad_add_dup_node.dtso- Extension
.dtso- Size
- 502 bytes
- Lines
- 28
- Domain
- Driver Families
- Bucket
- drivers/of
- Inferred role
- Driver Families: drivers/of
- Status
- atlas-only
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
/plugin/;
/*
* &electric_1/motor-1 and &spin_ctrl_1 are the same node:
* /testcase-data-2/substation@100/motor-1
*
* Thus the new node "controller" in each fragment will
* result in an attempt to add the same node twice.
* This will result in an error and the overlay apply
* will fail.
*/
&electric_1 {
motor-1 {
controller {
power_bus = <0x1 0x2>;
};
};
};
&spin_ctrl_1 {
controller {
power_bus_emergency = <0x101 0x102>;
};
};
Annotation
- Atlas domain: Driver Families / drivers/of.
- Implementation status: atlas-only.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.