drivers/parisc/ccio-dma.c
Source file repositories/reference/linux-study-clean/drivers/parisc/ccio-dma.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/parisc/ccio-dma.c- Extension
.c- Size
- 47463 bytes
- Lines
- 1587
- Domain
- Driver Families
- Bucket
- drivers/parisc
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/types.hlinux/kernel.hlinux/init.hlinux/mm.hlinux/spinlock.hlinux/slab.hlinux/string.hlinux/pci.hlinux/reboot.hlinux/proc_fs.hlinux/seq_file.hlinux/dma-map-ops.hlinux/scatterlist.hlinux/iommu-helper.hlinux/export.hasm/byteorder.hasm/cache.hlinux/uaccess.hasm/page.hasm/dma.hasm/io.hasm/hardware.hasm/parisc-device.hiommu.hiommu-helpers.h
Detected Declarations
struct ioa_registersstruct iocfunction log2function ccio_free_rangefunction addressfunction ccio_clear_io_tlbfunction ccio_mark_invalidfunction ccio_dma_supportedfunction ccio_map_singlefunction ccio_map_physfunction ccio_unmap_physfunction ccio_allocfunction gsc_map_xxxfunction ccio_freefunction ccio_map_sgfunction ccio_unmap_sgfunction ccio_proc_infofunction ccio_proc_bitmap_infofunction ccio_find_iocfunction ccio_get_iommufunction ccio_cujo20_fixupfunction Javafunction ccio_ioc_initfunction ccio_init_resourcefunction ccio_init_resourcesfunction new_ioc_areafunction expand_ioc_areafunction IOCfunction ccio_request_resourcefunction chipfunction ccio_init
Annotated Snippet
struct ioa_registers {
/* Runway Supervisory Set */
int32_t unused1[12];
uint32_t io_command; /* Offset 12 */
uint32_t io_status; /* Offset 13 */
uint32_t io_control; /* Offset 14 */
int32_t unused2[1];
/* Runway Auxiliary Register Set */
uint32_t io_err_resp; /* Offset 0 */
uint32_t io_err_info; /* Offset 1 */
uint32_t io_err_req; /* Offset 2 */
uint32_t io_err_resp_hi; /* Offset 3 */
uint32_t io_tlb_entry_m; /* Offset 4 */
uint32_t io_tlb_entry_l; /* Offset 5 */
uint32_t unused3[1];
uint32_t io_pdir_base; /* Offset 7 */
uint32_t io_io_low_hv; /* Offset 8 */
uint32_t io_io_high_hv; /* Offset 9 */
uint32_t unused4[1];
uint32_t io_chain_id_mask; /* Offset 11 */
uint32_t unused5[2];
uint32_t io_io_low; /* Offset 14 */
uint32_t io_io_high; /* Offset 15 */
};
/*
** IOA Registers
** -------------
**
** Runway IO_CONTROL Register (+0x38)
**
** The Runway IO_CONTROL register controls the forwarding of transactions.
**
** | 0 ... 13 | 14 15 | 16 ... 21 | 22 | 23 24 | 25 ... 31 |
** | HV | TLB | reserved | HV | mode | reserved |
**
** o mode field indicates the address translation of transactions
** forwarded from Runway to GSC+:
** Mode Name Value Definition
** Off (default) 0 Opaque to matching addresses.
** Include 1 Transparent for matching addresses.
** Peek 3 Map matching addresses.
**
** + "Off" mode: Runway transactions which match the I/O range
** specified by the IO_IO_LOW/IO_IO_HIGH registers will be ignored.
** + "Include" mode: all addresses within the I/O range specified
** by the IO_IO_LOW and IO_IO_HIGH registers are transparently
** forwarded. This is the I/O Adapter's normal operating mode.
** + "Peek" mode: used during system configuration to initialize the
** GSC+ bus. Runway Write_Shorts in the address range specified by
** IO_IO_LOW and IO_IO_HIGH are forwarded through the I/O Adapter
** *AND* the GSC+ address is remapped to the Broadcast Physical
** Address space by setting the 14 high order address bits of the
** 32 bit GSC+ address to ones.
**
** o TLB field affects transactions which are forwarded from GSC+ to Runway.
** "Real" mode is the poweron default.
**
** TLB Mode Value Description
** Real 0 No TLB translation. Address is directly mapped and the
** virtual address is composed of selected physical bits.
** Error 1 Software fills the TLB manually.
** Normal 2 IOA fetches IO TLB misses from IO PDIR (in host memory).
**
**
** IO_IO_LOW_HV +0x60 (HV dependent)
** IO_IO_HIGH_HV +0x64 (HV dependent)
** IO_IO_LOW +0x78 (Architected register)
** IO_IO_HIGH +0x7c (Architected register)
**
** IO_IO_LOW and IO_IO_HIGH set the lower and upper bounds of the
** I/O Adapter address space, respectively.
**
** 0 ... 7 | 8 ... 15 | 16 ... 31 |
** 11111111 | 11111111 | address |
**
** Each LOW/HIGH pair describes a disjoint address space region.
** (2 per GSC+ port). Each incoming Runway transaction address is compared
** with both sets of LOW/HIGH registers. If the address is in the range
** greater than or equal to IO_IO_LOW and less than IO_IO_HIGH the transaction
** for forwarded to the respective GSC+ bus.
** Specify IO_IO_LOW equal to or greater than IO_IO_HIGH to avoid specifying
** an address space region.
**
** In order for a Runway address to reside within GSC+ extended address space:
** Runway Address [0:7] must identically compare to 8'b11111111
** Runway Address [8:11] must be equal to IO_IO_LOW(_HV)[16:19]
** Runway Address [12:23] must be greater than or equal to
** IO_IO_LOW(_HV)[20:31] and less than IO_IO_HIGH(_HV)[20:31].
Annotation
- Immediate include surface: `linux/types.h`, `linux/kernel.h`, `linux/init.h`, `linux/mm.h`, `linux/spinlock.h`, `linux/slab.h`, `linux/string.h`, `linux/pci.h`.
- Detected declarations: `struct ioa_registers`, `struct ioc`, `function log2`, `function ccio_free_range`, `function address`, `function ccio_clear_io_tlb`, `function ccio_mark_invalid`, `function ccio_dma_supported`, `function ccio_map_single`, `function ccio_map_phys`.
- Atlas domain: Driver Families / drivers/parisc.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.