drivers/pci/controller/cadence/pcie-cadence.h

Source file repositories/reference/linux-study-clean/drivers/pci/controller/cadence/pcie-cadence.h

File Facts

System
Linux kernel
Corpus path
drivers/pci/controller/cadence/pcie-cadence.h
Extension
.h
Size
15542 bytes
Lines
537
Domain
Representative Device Path
Bucket
PCIe NVMe Storage Path
Inferred role
Representative Device Path: implementation source
Status
source implementation candidate

Why This File Exists

Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.

Dependency Surface

Detected Declarations

Annotated Snippet

struct cdns_pcie_rp_ib_bar {
	u64 size;
	bool free;
};

struct cdns_pcie;
struct cdns_pcie_rc;

enum cdns_pcie_reg_bank {
	REG_BANK_RP,
	REG_BANK_IP_REG,
	REG_BANK_IP_CFG_CTRL_REG,
	REG_BANK_AXI_MASTER_COMMON,
	REG_BANK_AXI_MASTER,
	REG_BANK_AXI_SLAVE,
	REG_BANK_AXI_HLS,
	REG_BANK_AXI_RAS,
	REG_BANK_AXI_DTI,
	REG_BANKS_MAX,
};

struct cdns_pcie_ops {
	int     (*start_link)(struct cdns_pcie *pcie);
	void    (*stop_link)(struct cdns_pcie *pcie);
	bool    (*link_up)(struct cdns_pcie *pcie);
	u64     (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr);
};

/**
 * struct cdns_plat_pcie_of_data - Register bank offset for a platform
 * @is_rc: controller is a RC
 * @ip_reg_bank_offset: ip register bank start offset
 * @ip_cfg_ctrl_reg_offset: ip config control register start offset
 * @axi_mstr_common_offset: AXI master common register start offset
 * @axi_slave_offset: AXI slave start offset
 * @axi_master_offset: AXI master start offset
 * @axi_hls_offset: AXI HLS offset start
 * @axi_ras_offset: AXI RAS offset
 * @axi_dti_offset: AXI DTI offset
 */
struct cdns_plat_pcie_of_data {
	u32 is_rc:1;
	u32 ip_reg_bank_offset;
	u32 ip_cfg_ctrl_reg_offset;
	u32 axi_mstr_common_offset;
	u32 axi_slave_offset;
	u32 axi_master_offset;
	u32 axi_hls_offset;
	u32 axi_ras_offset;
	u32 axi_dti_offset;
};

/**
 * struct cdns_pcie - private data for Cadence PCIe controller drivers
 * @reg_base: IO mapped register base
 * @mem_res: start/end offsets in the physical system memory to map PCI accesses
 * @msg_res: Region for send message to map PCI accesses
 * @dev: PCIe controller
 * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint.
 * @phy_count: number of supported PHY devices
 * @phy: list of pointers to specific PHY control blocks
 * @link: list of pointers to corresponding device link representations
 * @ops: Platform-specific ops to control various inputs from Cadence PCIe
 *       wrapper
 * @cdns_pcie_reg_offsets: Register bank offsets for different SoC
 */
struct cdns_pcie {
	void __iomem		             *reg_base;
	struct resource		             *mem_res;
	struct resource                      *msg_res;
	struct device		             *dev;
	bool			             is_rc;
	int			             phy_count;
	struct phy		             **phy;
	struct device_link	             **link;
	const  struct cdns_pcie_ops          *ops;
	const  struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets;
};

/**
 * struct cdns_pcie_rc - private data for this PCIe Root Complex driver
 * @pcie: Cadence PCIe controller
 * @cfg_res: start/end offsets in the physical system memory to map PCI
 *           configuration space accesses
 * @cfg_base: IO mapped window to access the PCI configuration space of a
 *            single function at a time
 * @vendor_id: PCI vendor ID
 * @device_id: PCI device ID
 * @avail_ib_bar: Status of RP_BAR0, RP_BAR1 and RP_NO_BAR if it's free or
 *                available

Annotation

Implementation Notes