drivers/pci/controller/cadence/pcie-cadence-plat.c
Source file repositories/reference/linux-study-clean/drivers/pci/controller/cadence/pcie-cadence-plat.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/pci/controller/cadence/pcie-cadence-plat.c- Extension
.c- Size
- 4111 bytes
- Lines
- 180
- Domain
- Representative Device Path
- Bucket
- PCIe NVMe Storage Path
- Inferred role
- Representative Device Path: implementation source
- Status
- source implementation candidate
Why This File Exists
Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.
- Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kernel.hlinux/of.hlinux/of_pci.hlinux/platform_device.hlinux/pm_runtime.hpcie-cadence.h
Detected Declarations
struct cdns_plat_pciefunction cdns_plat_cpu_addr_fixupfunction cdns_plat_pcie_probefunction cdns_plat_pcie_shutdown
Annotated Snippet
struct cdns_plat_pcie {
struct cdns_pcie *pcie;
};
static const struct of_device_id cdns_plat_pcie_of_match[];
static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr)
{
return cpu_addr & CDNS_PLAT_CPU_TO_BUS_ADDR;
}
static const struct cdns_pcie_ops cdns_plat_ops = {
.cpu_addr_fixup = cdns_plat_cpu_addr_fixup,
};
static int cdns_plat_pcie_probe(struct platform_device *pdev)
{
const struct cdns_plat_pcie_of_data *data;
struct cdns_plat_pcie *cdns_plat_pcie;
struct device *dev = &pdev->dev;
struct pci_host_bridge *bridge;
struct cdns_pcie_ep *ep;
struct cdns_pcie_rc *rc;
int phy_count;
bool is_rc;
int ret;
data = of_device_get_match_data(dev);
if (!data)
return -EINVAL;
is_rc = data->is_rc;
pr_debug(" Started %s with is_rc: %d\n", __func__, is_rc);
cdns_plat_pcie = devm_kzalloc(dev, sizeof(*cdns_plat_pcie), GFP_KERNEL);
if (!cdns_plat_pcie)
return -ENOMEM;
platform_set_drvdata(pdev, cdns_plat_pcie);
if (is_rc) {
if (!IS_ENABLED(CONFIG_PCIE_CADENCE_PLAT_HOST))
return -ENODEV;
bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
if (!bridge)
return -ENOMEM;
rc = pci_host_bridge_priv(bridge);
rc->pcie.dev = dev;
rc->pcie.ops = &cdns_plat_ops;
cdns_plat_pcie->pcie = &rc->pcie;
ret = cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie);
if (ret) {
dev_err(dev, "failed to init phy\n");
return ret;
}
pm_runtime_enable(dev);
ret = pm_runtime_get_sync(dev);
if (ret < 0) {
dev_err(dev, "pm_runtime_get_sync() failed\n");
goto err_get_sync;
}
ret = cdns_pcie_host_setup(rc);
if (ret)
goto err_init;
} else {
if (!IS_ENABLED(CONFIG_PCIE_CADENCE_PLAT_EP))
return -ENODEV;
ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
if (!ep)
return -ENOMEM;
ep->pcie.dev = dev;
ep->pcie.ops = &cdns_plat_ops;
cdns_plat_pcie->pcie = &ep->pcie;
ret = cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie);
if (ret) {
dev_err(dev, "failed to init phy\n");
return ret;
}
pm_runtime_enable(dev);
ret = pm_runtime_get_sync(dev);
if (ret < 0) {
dev_err(dev, "pm_runtime_get_sync() failed\n");
goto err_get_sync;
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/of.h`, `linux/of_pci.h`, `linux/platform_device.h`, `linux/pm_runtime.h`, `pcie-cadence.h`.
- Detected declarations: `struct cdns_plat_pcie`, `function cdns_plat_cpu_addr_fixup`, `function cdns_plat_pcie_probe`, `function cdns_plat_pcie_shutdown`.
- Atlas domain: Representative Device Path / PCIe NVMe Storage Path.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.