drivers/pci/controller/dwc/pcie-andes-qilai.c

Source file repositories/reference/linux-study-clean/drivers/pci/controller/dwc/pcie-andes-qilai.c

File Facts

System
Linux kernel
Corpus path
drivers/pci/controller/dwc/pcie-andes-qilai.c
Extension
.c
Size
5258 bytes
Lines
198
Domain
Representative Device Path
Bucket
PCIe NVMe Storage Path
Inferred role
Representative Device Path: implementation source
Status
source implementation candidate

Why This File Exists

Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.

Dependency Surface

Detected Declarations

Annotated Snippet

struct qilai_pcie {
	struct dw_pcie pci;
	void __iomem *apb_base;
};

#define to_qilai_pcie(_pci) container_of(_pci, struct qilai_pcie, pci)

static bool qilai_pcie_link_up(struct dw_pcie *pci)
{
	struct qilai_pcie *pcie = to_qilai_pcie(pci);
	u32 val;

	val = readl(pcie->apb_base + PCIE_REGS_PCIE_SII_PM_STATE);

	return FIELD_GET(SMLH_LINK_UP, val) && FIELD_GET(RDLH_LINK_UP, val);
}

static int qilai_pcie_start_link(struct dw_pcie *pci)
{
	struct qilai_pcie *pcie = to_qilai_pcie(pci);
	u32 val;

	val = readl(pcie->apb_base + PCIE_GEN_CONTROL2);
	val |= PCIE_CFG_LTSSM_EN;
	writel(val, pcie->apb_base + PCIE_GEN_CONTROL2);

	return 0;
}

static const struct dw_pcie_ops qilai_pcie_ops = {
	.link_up = qilai_pcie_link_up,
	.start_link = qilai_pcie_start_link,
};

/*
 * Set up the QiLai PCIe IOCP (IO Coherence Port) Read/Write Behaviors to the
 * Write-Back, Read and Write Allocate mode.
 *
 * The IOCP HW target is SoC last-level cache (L2 Cache), which serves as the
 * system cache. The IOCP HW helps maintain cache monitoring, ensuring that
 * the device can snoop data from/to the cache.
 */
static void qilai_pcie_iocp_cache_setup(struct dw_pcie_rp *pp)
{
	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
	u32 val;

	dw_pcie_dbi_ro_wr_en(pci);

	val = dw_pcie_readl_dbi(pci, PCIE_LOGIC_COHERENCY_CONTROL3);
	FIELD_MODIFY(PCIE_CFG_MSTR_ARCACHE_MODE, &val, IOCP_ARCACHE);
	FIELD_MODIFY(PCIE_CFG_MSTR_AWCACHE_MODE, &val, IOCP_AWCACHE);
	FIELD_MODIFY(PCIE_CFG_MSTR_ARCACHE_VALUE, &val, IOCP_ARCACHE);
	FIELD_MODIFY(PCIE_CFG_MSTR_AWCACHE_VALUE, &val, IOCP_AWCACHE);
	dw_pcie_writel_dbi(pci, PCIE_LOGIC_COHERENCY_CONTROL3, val);

	dw_pcie_dbi_ro_wr_dis(pci);
}

static void qilai_pcie_enable_msi(struct qilai_pcie *pcie)
{
	u32 val;

	val = readl(pcie->apb_base + PCIE_INTR_CONTROL1);
	val |= PCIE_MSI_CTRL_INT_EN;
	writel(val, pcie->apb_base + PCIE_INTR_CONTROL1);
}

static int qilai_pcie_host_init(struct dw_pcie_rp *pp)
{
	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
	struct qilai_pcie *pcie = to_qilai_pcie(pci);

	qilai_pcie_enable_msi(pcie);

	return 0;
}

static void qilai_pcie_host_post_init(struct dw_pcie_rp *pp)
{
	qilai_pcie_iocp_cache_setup(pp);
}

static const struct dw_pcie_host_ops qilai_pcie_host_ops = {
	.init = qilai_pcie_host_init,
	.post_init = qilai_pcie_host_post_init,
};

static int qilai_pcie_probe(struct platform_device *pdev)
{

Annotation

Implementation Notes