drivers/pci/controller/dwc/pcie-armada8k.c
Source file repositories/reference/linux-study-clean/drivers/pci/controller/dwc/pcie-armada8k.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/pci/controller/dwc/pcie-armada8k.c- Extension
.c- Size
- 8745 bytes
- Lines
- 350
- Domain
- Representative Device Path
- Bucket
- PCIe NVMe Storage Path
- Inferred role
- Representative Device Path: implementation source
- Status
- source implementation candidate
Why This File Exists
Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.
- Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/clk.hlinux/delay.hlinux/interrupt.hlinux/kernel.hlinux/init.hlinux/of.hlinux/pci.hlinux/phy/phy.hlinux/platform_device.hlinux/resource.hlinux/of_pci.hpcie-designware.h
Detected Declarations
struct armada8k_pciefunction armada8k_pcie_disable_physfunction armada8k_pcie_enable_physfunction armada8k_pcie_setup_physfunction armada8k_pcie_link_upfunction armada8k_pcie_start_linkfunction armada8k_pcie_host_initfunction armada8k_pcie_irq_handlerfunction armada8k_add_pcie_portfunction armada8k_pcie_probe
Annotated Snippet
struct armada8k_pcie {
struct dw_pcie *pci;
struct clk *clk;
struct clk *clk_reg;
struct phy *phy[ARMADA8K_PCIE_MAX_LANES];
unsigned int phy_count;
};
#define PCIE_VENDOR_REGS_OFFSET 0x8000
#define PCIE_GLOBAL_CONTROL_REG (PCIE_VENDOR_REGS_OFFSET + 0x0)
#define PCIE_APP_LTSSM_EN BIT(2)
#define PCIE_DEVICE_TYPE_SHIFT 4
#define PCIE_DEVICE_TYPE_MASK 0xF
#define PCIE_DEVICE_TYPE_RC 0x4 /* Root complex */
#define PCIE_GLOBAL_STATUS_REG (PCIE_VENDOR_REGS_OFFSET + 0x8)
#define PCIE_GLB_STS_RDLH_LINK_UP BIT(1)
#define PCIE_GLB_STS_PHY_LINK_UP BIT(9)
#define PCIE_GLOBAL_INT_CAUSE1_REG (PCIE_VENDOR_REGS_OFFSET + 0x1C)
#define PCIE_GLOBAL_INT_MASK1_REG (PCIE_VENDOR_REGS_OFFSET + 0x20)
#define PCIE_INT_A_ASSERT_MASK BIT(9)
#define PCIE_INT_B_ASSERT_MASK BIT(10)
#define PCIE_INT_C_ASSERT_MASK BIT(11)
#define PCIE_INT_D_ASSERT_MASK BIT(12)
#define PCIE_ARCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x50)
#define PCIE_AWCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x54)
#define PCIE_ARUSER_REG (PCIE_VENDOR_REGS_OFFSET + 0x5C)
#define PCIE_AWUSER_REG (PCIE_VENDOR_REGS_OFFSET + 0x60)
/*
* AR/AW Cache defaults: Normal memory, Write-Back, Read / Write
* allocate
*/
#define ARCACHE_DEFAULT_VALUE 0x3511
#define AWCACHE_DEFAULT_VALUE 0x5311
#define DOMAIN_OUTER_SHAREABLE 0x2
#define AX_USER_DOMAIN_MASK 0x3
#define AX_USER_DOMAIN_SHIFT 4
#define to_armada8k_pcie(x) dev_get_drvdata((x)->dev)
static void armada8k_pcie_disable_phys(struct armada8k_pcie *pcie)
{
int i;
for (i = 0; i < ARMADA8K_PCIE_MAX_LANES; i++) {
phy_power_off(pcie->phy[i]);
phy_exit(pcie->phy[i]);
}
}
static int armada8k_pcie_enable_phys(struct armada8k_pcie *pcie)
{
int ret;
int i;
for (i = 0; i < ARMADA8K_PCIE_MAX_LANES; i++) {
ret = phy_init(pcie->phy[i]);
if (ret)
return ret;
ret = phy_set_mode_ext(pcie->phy[i], PHY_MODE_PCIE,
pcie->phy_count);
if (ret) {
phy_exit(pcie->phy[i]);
return ret;
}
ret = phy_power_on(pcie->phy[i]);
if (ret) {
phy_exit(pcie->phy[i]);
return ret;
}
}
return 0;
}
static int armada8k_pcie_setup_phys(struct armada8k_pcie *pcie)
{
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
struct device_node *node = dev->of_node;
int ret = 0;
int i;
for (i = 0; i < ARMADA8K_PCIE_MAX_LANES; i++) {
Annotation
- Immediate include surface: `linux/clk.h`, `linux/delay.h`, `linux/interrupt.h`, `linux/kernel.h`, `linux/init.h`, `linux/of.h`, `linux/pci.h`, `linux/phy/phy.h`.
- Detected declarations: `struct armada8k_pcie`, `function armada8k_pcie_disable_phys`, `function armada8k_pcie_enable_phys`, `function armada8k_pcie_setup_phys`, `function armada8k_pcie_link_up`, `function armada8k_pcie_start_link`, `function armada8k_pcie_host_init`, `function armada8k_pcie_irq_handler`, `function armada8k_add_pcie_port`, `function armada8k_pcie_probe`.
- Atlas domain: Representative Device Path / PCIe NVMe Storage Path.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.