drivers/pci/controller/dwc/pcie-designware-debugfs.c
Source file repositories/reference/linux-study-clean/drivers/pci/controller/dwc/pcie-designware-debugfs.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/pci/controller/dwc/pcie-designware-debugfs.c- Extension
.c- Size
- 27061 bytes
- Lines
- 931
- Domain
- Representative Device Path
- Bucket
- PCIe NVMe Storage Path
- Inferred role
- Representative Device Path: operation-table or driver-model contract
- Status
- pattern implementation candidate
Why This File Exists
Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.
- Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.
- Defines an operation table; this is where Linux turns generic core objects into subsystem-specific behavior.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/debugfs.hpcie-designware.h
Detected Declarations
struct dwc_pcie_rasdes_infostruct dwc_pcie_rasdes_privstruct dwc_pcie_err_injstruct dwc_pcie_event_counterfunction lane_detect_readfunction lane_detect_writefunction rx_valid_readfunction rx_valid_writefunction err_inj_writefunction set_event_numberfunction counter_enable_readfunction counter_enable_writefunction counter_lane_readfunction counter_lane_writefunction counter_value_readfunction ltssm_status_showfunction ltssm_status_openfunction dwc_pcie_rasdes_debugfs_deinitfunction dwc_pcie_rasdes_debugfs_initfunction dwc_pcie_ltssm_debugfs_initfunction dw_pcie_ptm_check_capabilityfunction dw_pcie_ptm_context_update_writefunction dw_pcie_ptm_context_update_readfunction dw_pcie_ptm_context_valid_writefunction dw_pcie_ptm_context_valid_readfunction dw_pcie_ptm_local_clock_readfunction dw_pcie_ptm_master_clock_readfunction dw_pcie_ptm_t1_readfunction dw_pcie_ptm_t2_readfunction dw_pcie_ptm_t3_readfunction dw_pcie_ptm_t4_readfunction dw_pcie_ptm_context_update_visiblefunction dw_pcie_ptm_context_valid_visiblefunction dw_pcie_ptm_local_clock_visiblefunction dw_pcie_ptm_master_clock_visiblefunction dw_pcie_ptm_t1_visiblefunction dw_pcie_ptm_t2_visiblefunction dw_pcie_ptm_t3_visiblefunction dw_pcie_ptm_t4_visiblefunction dwc_pcie_debugfs_deinitfunction dwc_pcie_debugfs_init
Annotated Snippet
static const struct file_operations dbg_ ## name ## _fops = { \
.open = simple_open, \
.read = name ## _read, \
.write = name ## _write \
}
DWC_DEBUGFS_FOPS(lane_detect);
DWC_DEBUGFS_FOPS(rx_valid);
static const struct file_operations dwc_pcie_err_inj_ops = {
.open = simple_open,
.write = err_inj_write,
};
static const struct file_operations dwc_pcie_counter_enable_ops = {
.open = simple_open,
.read = counter_enable_read,
.write = counter_enable_write,
};
static const struct file_operations dwc_pcie_counter_lane_ops = {
.open = simple_open,
.read = counter_lane_read,
.write = counter_lane_write,
};
static const struct file_operations dwc_pcie_counter_value_ops = {
.open = simple_open,
.read = counter_value_read,
};
static const struct file_operations dwc_pcie_ltssm_status_ops = {
.open = ltssm_status_open,
.read = seq_read,
};
static void dwc_pcie_rasdes_debugfs_deinit(struct dw_pcie *pci)
{
struct dwc_pcie_rasdes_info *rinfo = pci->debugfs->rasdes_info;
mutex_destroy(&rinfo->reg_event_lock);
}
static int dwc_pcie_rasdes_debugfs_init(struct dw_pcie *pci, struct dentry *dir)
{
struct dentry *rasdes_debug, *rasdes_err_inj;
struct dentry *rasdes_event_counter, *rasdes_events;
struct dwc_pcie_rasdes_info *rasdes_info;
struct dwc_pcie_rasdes_priv *priv_tmp;
struct device *dev = pci->dev;
int ras_cap, i, ret;
/*
* If a given SoC has no RAS DES capability, the following call is
* bound to return an error, breaking some existing platforms. So,
* return 0 here, as this is not necessarily an error.
*/
ras_cap = dw_pcie_find_rasdes_capability(pci);
if (!ras_cap) {
dev_dbg(dev, "no RAS DES capability available\n");
return 0;
}
rasdes_info = devm_kzalloc(dev, sizeof(*rasdes_info), GFP_KERNEL);
if (!rasdes_info)
return -ENOMEM;
/* Create subdirectories for Debug, Error Injection, Statistics. */
rasdes_debug = debugfs_create_dir("rasdes_debug", dir);
rasdes_err_inj = debugfs_create_dir("rasdes_err_inj", dir);
rasdes_event_counter = debugfs_create_dir("rasdes_event_counter", dir);
mutex_init(&rasdes_info->reg_event_lock);
rasdes_info->ras_cap_offset = ras_cap;
pci->debugfs->rasdes_info = rasdes_info;
/* Create debugfs files for Debug subdirectory. */
dwc_debugfs_create(lane_detect);
dwc_debugfs_create(rx_valid);
/* Create debugfs files for Error Injection subdirectory. */
for (i = 0; i < ARRAY_SIZE(err_inj_list); i++) {
priv_tmp = devm_kzalloc(dev, sizeof(*priv_tmp), GFP_KERNEL);
if (!priv_tmp) {
ret = -ENOMEM;
goto err_deinit;
}
priv_tmp->idx = i;
priv_tmp->pci = pci;
Annotation
- Immediate include surface: `linux/debugfs.h`, `pcie-designware.h`.
- Detected declarations: `struct dwc_pcie_rasdes_info`, `struct dwc_pcie_rasdes_priv`, `struct dwc_pcie_err_inj`, `struct dwc_pcie_event_counter`, `function lane_detect_read`, `function lane_detect_write`, `function rx_valid_read`, `function rx_valid_write`, `function err_inj_write`, `function set_event_number`.
- Atlas domain: Representative Device Path / PCIe NVMe Storage Path.
- Implementation status: pattern implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.