drivers/pci/controller/dwc/pcie-designware.h

Source file repositories/reference/linux-study-clean/drivers/pci/controller/dwc/pcie-designware.h

File Facts

System
Linux kernel
Corpus path
drivers/pci/controller/dwc/pcie-designware.h
Extension
.h
Size
29255 bytes
Lines
992
Domain
Representative Device Path
Bucket
PCIe NVMe Storage Path
Inferred role
Representative Device Path: implementation source
Status
source implementation candidate

Why This File Exists

Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dw_pcie_ob_atu_cfg {
	int index;
	int type;
	u8 func_no;
	u8 code;
	u8 routing;
	u32 ctrl2;
	u64 parent_bus_addr;
	u64 pci_addr;
	u64 size;
};

struct dw_pcie_host_ops {
	int (*init)(struct dw_pcie_rp *pp);
	void (*deinit)(struct dw_pcie_rp *pp);
	void (*post_init)(struct dw_pcie_rp *pp);
	int (*msi_init)(struct dw_pcie_rp *pp);
	void (*pme_turn_off)(struct dw_pcie_rp *pp);
};

struct dw_pcie_rp {
	bool			use_imsi_rx:1;
	bool			keep_rp_msi_en:1;
	bool			cfg0_io_shared:1;
	u64			cfg0_base;
	void __iomem		*va_cfg0_base;
	u32			cfg0_size;
	resource_size_t		io_base;
	phys_addr_t		io_bus_addr;
	u32			io_size;
	int			irq;
	const struct dw_pcie_host_ops *ops;
	int			msi_irq[MAX_MSI_CTRLS];
	struct irq_domain	*irq_domain;
	dma_addr_t		msi_data;
	struct irq_chip		*msi_irq_chip;
	u32			num_vectors;
	u32			irq_mask[MAX_MSI_CTRLS];
	struct pci_host_bridge  *bridge;
	raw_spinlock_t		lock;
	DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
	bool			use_atu_msg;
	int			msg_atu_index;
	struct resource		*msg_res;
	struct pci_eq_presets	presets;
	struct pci_config_window *cfg;
	bool			ecam_enabled;
	bool			native_ecam;
	bool                    skip_l23_ready;
};

struct dw_pcie_ep_ops {
	void	(*pre_init)(struct dw_pcie_ep *ep);
	void	(*init)(struct dw_pcie_ep *ep);
	int	(*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
			     unsigned int type, u16 interrupt_num);
	const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
	/*
	 * Provide a method to implement the different func config space
	 * access for different platform, if different func have different
	 * offset, return the offset of func. if use write a register way
	 * return a 0, and implement code in callback function of platform
	 * driver.
	 */
	unsigned int (*get_dbi_offset)(struct dw_pcie_ep *ep, u8 func_no);
	unsigned int (*get_dbi2_offset)(struct dw_pcie_ep *ep, u8 func_no);
};

struct dw_pcie_ep_func {
	struct list_head	list;
	u8			func_no;
	u8			msi_cap;	/* MSI capability offset */
	u8			msix_cap;	/* MSI-X capability offset */
	u8			bar_to_atu[PCI_STD_NUM_BARS];
	struct pci_epf_bar	*epf_bar[PCI_STD_NUM_BARS];

	/* Only for Address Match Mode inbound iATU */
	u32			*ib_atu_indexes[PCI_STD_NUM_BARS];
	unsigned int		num_ib_atu_indexes[PCI_STD_NUM_BARS];
};

struct dw_pcie_ep {
	struct pci_epc		*epc;
	struct list_head	func_list;
	const struct dw_pcie_ep_ops *ops;
	phys_addr_t		phys_base;
	size_t			addr_size;
	size_t			page_size;
	phys_addr_t		*outbound_addr;
	unsigned long		*ib_window_map;

Annotation

Implementation Notes