drivers/pci/controller/dwc/pcie-tegra194.c

Source file repositories/reference/linux-study-clean/drivers/pci/controller/dwc/pcie-tegra194.c

File Facts

System
Linux kernel
Corpus path
drivers/pci/controller/dwc/pcie-tegra194.c
Extension
.c
Size
72110 bytes
Lines
2579
Domain
Representative Device Path
Bucket
PCIe NVMe Storage Path
Inferred role
Representative Device Path: implementation source
Status
source implementation candidate

Why This File Exists

Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.

Dependency Surface

Detected Declarations

Annotated Snippet

struct tegra_pcie_dw_of_data {
	u32 version;
	enum dw_pcie_device_mode mode;
	bool has_msix_doorbell_access_fix;
	bool has_sbr_reset_fix;
	bool has_l1ss_exit_fix;
	bool has_ltr_req_fix;
	bool disable_l1_2;
	u32 cdm_chk_int_en_bit;
	u32 gen4_preset_vec;
	u8 n_fts[2];
};

struct tegra_pcie_dw {
	struct device *dev;
	struct resource *appl_res;
	struct resource *dbi_res;
	struct resource *atu_dma_res;
	void __iomem *appl_base;
	struct clk *core_clk;
	struct clk *core_clk_m;
	struct reset_control *core_apb_rst;
	struct reset_control *core_rst;
	struct dw_pcie pci;
	struct tegra_bpmp *bpmp;

	struct tegra_pcie_dw_of_data *of_data;

	bool supports_clkreq;
	bool enable_cdm_check;
	bool enable_srns;
	bool link_state;
	bool update_fc_fixup;
	bool enable_ext_refclk;
	u8 init_link_width;
	u32 msi_ctrl_int;
	u32 num_lanes;
	u32 cid;
	u32 ras_des_cap;
	u32 pcie_cap_base;
	u32 aspm_cmrt;
	u32 aspm_pwr_on_t;
	u32 aspm_l0s_enter_lat;

	struct regulator *pex_ctl_supply;
	struct regulator *slot_ctl_3v3;
	struct regulator *slot_ctl_12v;

	unsigned int phy_count;
	struct phy **phys;

	struct dentry *debugfs;

	/* Endpoint mode specific */
	struct gpio_desc *pex_rst_gpiod;
	struct gpio_desc *pex_refclk_sel_gpiod;
	unsigned int pex_rst_irq;
	int ep_state;
	long link_status;
	struct icc_path *icc_path;
};

static inline struct tegra_pcie_dw *to_tegra_pcie(struct dw_pcie *pci)
{
	return container_of(pci, struct tegra_pcie_dw, pci);
}

static inline void appl_writel(struct tegra_pcie_dw *pcie, const u32 value,
			       const u32 reg)
{
	writel_relaxed(value, pcie->appl_base + reg);
}

static inline u32 appl_readl(struct tegra_pcie_dw *pcie, const u32 reg)
{
	return readl_relaxed(pcie->appl_base + reg);
}

static void tegra_pcie_icc_set(struct tegra_pcie_dw *pcie)
{
	struct dw_pcie *pci = &pcie->pci;
	u32 val, speed, width;

	val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);

	speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, val);
	width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val);

	val = width * PCIE_SPEED2MBS_ENC(pcie_get_link_speed(speed));

Annotation

Implementation Notes