drivers/pci/controller/dwc/pcie-uniphier.c

Source file repositories/reference/linux-study-clean/drivers/pci/controller/dwc/pcie-uniphier.c

File Facts

System
Linux kernel
Corpus path
drivers/pci/controller/dwc/pcie-uniphier.c
Extension
.c
Size
10066 bytes
Lines
410
Domain
Representative Device Path
Bucket
PCIe NVMe Storage Path
Inferred role
Representative Device Path: implementation source
Status
source implementation candidate

Why This File Exists

Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.

Dependency Surface

Detected Declarations

Annotated Snippet

struct uniphier_pcie {
	struct dw_pcie pci;
	void __iomem *base;
	struct clk *clk;
	struct reset_control *rst;
	struct phy *phy;
	struct irq_domain *intx_irq_domain;
};

#define to_uniphier_pcie(x)	dev_get_drvdata((x)->dev)

static void uniphier_pcie_ltssm_enable(struct uniphier_pcie *pcie,
				       bool enable)
{
	u32 val;

	val = readl(pcie->base + PCL_APP_READY_CTRL);
	if (enable)
		val |= PCL_APP_LTSSM_ENABLE;
	else
		val &= ~PCL_APP_LTSSM_ENABLE;
	writel(val, pcie->base + PCL_APP_READY_CTRL);
}

static void uniphier_pcie_init_rc(struct uniphier_pcie *pcie)
{
	u32 val;

	/* set RC MODE */
	val = readl(pcie->base + PCL_MODE);
	val |= PCL_MODE_REGEN;
	val &= ~PCL_MODE_REGVAL;
	writel(val, pcie->base + PCL_MODE);

	/* use auxiliary power detection */
	val = readl(pcie->base + PCL_APP_PM0);
	val |= PCL_SYS_AUX_PWR_DET;
	writel(val, pcie->base + PCL_APP_PM0);

	/* assert PERST# */
	val = readl(pcie->base + PCL_PINCTRL0);
	val &= ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL
		 | PCL_PERST_PLDN_REGVAL);
	val |= PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN
		| PCL_PERST_PLDN_REGEN;
	writel(val, pcie->base + PCL_PINCTRL0);

	uniphier_pcie_ltssm_enable(pcie, false);

	usleep_range(100000, 200000);

	/* deassert PERST# */
	val = readl(pcie->base + PCL_PINCTRL0);
	val |= PCL_PERST_OUT_REGVAL | PCL_PERST_OUT_REGEN;
	writel(val, pcie->base + PCL_PINCTRL0);
}

static int uniphier_pcie_wait_rc(struct uniphier_pcie *pcie)
{
	u32 status;
	int ret;

	/* wait PIPE clock */
	ret = readl_poll_timeout(pcie->base + PCL_PIPEMON, status,
				 status & PCL_PCLK_ALIVE, 100000, 1000000);
	if (ret) {
		dev_err(pcie->pci.dev,
			"Failed to initialize controller in RC mode\n");
		return ret;
	}

	return 0;
}

static bool uniphier_pcie_link_up(struct dw_pcie *pci)
{
	struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
	u32 val, mask;

	val = readl(pcie->base + PCL_STATUS_LINK);
	mask = PCL_RDLH_LINK_UP | PCL_XMLH_LINK_UP;

	return (val & mask) == mask;
}

static int uniphier_pcie_start_link(struct dw_pcie *pci)
{
	struct uniphier_pcie *pcie = to_uniphier_pcie(pci);

	uniphier_pcie_ltssm_enable(pcie, true);

Annotation

Implementation Notes