drivers/pci/controller/dwc/pcie-uniphier-ep.c

Source file repositories/reference/linux-study-clean/drivers/pci/controller/dwc/pcie-uniphier-ep.c

File Facts

System
Linux kernel
Corpus path
drivers/pci/controller/dwc/pcie-uniphier-ep.c
Extension
.c
Size
11064 bytes
Lines
462
Domain
Representative Device Path
Bucket
PCIe NVMe Storage Path
Inferred role
Representative Device Path: implementation source
Status
source implementation candidate

Why This File Exists

Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.

Dependency Surface

Detected Declarations

Annotated Snippet

struct uniphier_pcie_ep_priv {
	void __iomem *base;
	struct dw_pcie pci;
	struct clk *clk, *clk_gio;
	struct reset_control *rst, *rst_gio;
	struct phy *phy;
	const struct uniphier_pcie_ep_soc_data *data;
};

struct uniphier_pcie_ep_soc_data {
	bool has_gio;
	void (*init)(struct uniphier_pcie_ep_priv *priv);
	int (*wait)(struct uniphier_pcie_ep_priv *priv);
	const struct pci_epc_features features;
};

#define to_uniphier_pcie(x)	dev_get_drvdata((x)->dev)

static void uniphier_pcie_ltssm_enable(struct uniphier_pcie_ep_priv *priv,
				       bool enable)
{
	u32 val;

	val = readl(priv->base + PCL_APP_READY_CTRL);
	if (enable)
		val |= PCL_APP_LTSSM_ENABLE;
	else
		val &= ~PCL_APP_LTSSM_ENABLE;
	writel(val, priv->base + PCL_APP_READY_CTRL);
}

static void uniphier_pcie_phy_reset(struct uniphier_pcie_ep_priv *priv,
				    bool assert)
{
	u32 val;

	val = readl(priv->base + PCL_RSTCTRL2);
	if (assert)
		val |= PCL_RSTCTRL_PHY_RESET;
	else
		val &= ~PCL_RSTCTRL_PHY_RESET;
	writel(val, priv->base + PCL_RSTCTRL2);
}

static void uniphier_pcie_pro5_init_ep(struct uniphier_pcie_ep_priv *priv)
{
	u32 val;

	/* set EP mode */
	val = readl(priv->base + PCL_MODE);
	val |= PCL_MODE_REGEN | PCL_MODE_REGVAL;
	writel(val, priv->base + PCL_MODE);

	/* clock request */
	val = readl(priv->base + PCL_APP_CLK_CTRL);
	val &= ~PCL_APP_CLK_REQ;
	writel(val, priv->base + PCL_APP_CLK_CTRL);

	/* deassert PIPE3 and AXI reset */
	val = readl(priv->base + PCL_RSTCTRL0);
	val |= PCL_RSTCTRL_AXI_REG | PCL_RSTCTRL_AXI_SLAVE
		| PCL_RSTCTRL_AXI_MASTER | PCL_RSTCTRL_PIPE3;
	writel(val, priv->base + PCL_RSTCTRL0);

	uniphier_pcie_ltssm_enable(priv, false);

	msleep(100);
}

static void uniphier_pcie_nx1_init_ep(struct uniphier_pcie_ep_priv *priv)
{
	u32 val;

	/* set EP mode */
	val = readl(priv->base + PCL_MODE);
	val |= PCL_MODE_REGEN | PCL_MODE_REGVAL;
	writel(val, priv->base + PCL_MODE);

	/* use auxiliary power detection */
	val = readl(priv->base + PCL_APP_PM0);
	val |= PCL_SYS_AUX_PWR_DET;
	writel(val, priv->base + PCL_APP_PM0);

	/* assert PERST# */
	val = readl(priv->base + PCL_PINCTRL0);
	val &= ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL
		 | PCL_PERST_PLDN_REGVAL);
	val |= PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN
		| PCL_PERST_PLDN_REGEN;
	writel(val, priv->base + PCL_PINCTRL0);

Annotation

Implementation Notes