drivers/pci/controller/pci-hyperv.c
Source file repositories/reference/linux-study-clean/drivers/pci/controller/pci-hyperv.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/pci/controller/pci-hyperv.c- Extension
.c- Size
- 118847 bytes
- Lines
- 4195
- Domain
- Representative Device Path
- Bucket
- PCIe NVMe Storage Path
- Inferred role
- Representative Device Path: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.
- Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kernel.hlinux/module.hlinux/pci.hlinux/pci-ecam.hlinux/delay.hlinux/semaphore.hlinux/irq.hlinux/irqchip/irq-msi-lib.hlinux/msi.hlinux/hyperv.hlinux/refcount.hlinux/irqdomain.hlinux/acpi.hlinux/sizes.hlinux/of_irq.hasm/mshyperv.h
Detected Declarations
struct pci_function_descriptionstruct pci_function_description2struct hv_msi_descstruct hv_msi_desc2struct hv_msi_desc3struct tran_int_descstruct pci_messagestruct pci_child_messagestruct pci_incoming_messagestruct pci_responsestruct pci_packetstruct pci_version_requeststruct pci_bus_d0_entrystruct pci_bus_relationsstruct pci_bus_relations2struct pci_q_res_req_responsestruct pci_set_powerstruct pci_set_power_responsestruct pci_resources_assignedstruct pci_resources_assigned2struct pci_create_interruptstruct pci_create_int_responsestruct pci_create_interrupt2struct pci_create_interrupt3struct pci_delete_interruptstruct pci_read_blockstruct pci_read_block_responsestruct pci_write_blockstruct pci_dev_inval_blockstruct pci_dev_incomingstruct pci_eject_responsestruct hv_pcibus_devicestruct hv_dr_workstruct hv_pcidev_descriptionstruct hv_dr_statestruct hv_pci_devstruct hv_pci_complstruct hv_pci_chip_datastruct hv_read_config_complstruct compose_comp_ctxtstruct q_res_req_complenum pci_protocol_version_tenum pci_message_typeenum pci_device_description_flagsenum hv_pcibus_statefunction hv_pci_irqchip_initfunction hv_msi_get_int_vectorfunction hv_irq_retarget_interrupt
Annotated Snippet
module_init(init_hv_pci_drv);
module_exit(exit_hv_pci_drv);
MODULE_DESCRIPTION("Hyper-V PCI");
MODULE_LICENSE("GPL v2");
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/module.h`, `linux/pci.h`, `linux/pci-ecam.h`, `linux/delay.h`, `linux/semaphore.h`, `linux/irq.h`, `linux/irqchip/irq-msi-lib.h`.
- Detected declarations: `struct pci_function_description`, `struct pci_function_description2`, `struct hv_msi_desc`, `struct hv_msi_desc2`, `struct hv_msi_desc3`, `struct tran_int_desc`, `struct pci_message`, `struct pci_child_message`, `struct pci_incoming_message`, `struct pci_response`.
- Atlas domain: Representative Device Path / PCIe NVMe Storage Path.
- Implementation status: integration implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.