drivers/pci/controller/pci-mvebu.c
Source file repositories/reference/linux-study-clean/drivers/pci/controller/pci-mvebu.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/pci/controller/pci-mvebu.c- Extension
.c- Size
- 49197 bytes
- Lines
- 1716
- Domain
- Representative Device Path
- Bucket
- PCIe NVMe Storage Path
- Inferred role
- Representative Device Path: implementation source
- Status
- source implementation candidate
Why This File Exists
Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.
- Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kernel.hlinux/module.hlinux/pci.hlinux/bitfield.hlinux/clk.hlinux/delay.hlinux/gpio/consumer.hlinux/init.hlinux/irqchip/chained_irq.hlinux/irqdomain.hlinux/mbus.hlinux/slab.hlinux/platform_device.hlinux/of_address.hlinux/of_irq.hlinux/of_pci.hlinux/of_platform.h../pci.h../pci-bridge-emul.h
Detected Declarations
struct mvebu_pcie_portstruct mvebu_pciestruct mvebu_pcie_windowstruct mvebu_pcie_portfunction mvebu_writelfunction mvebu_readlfunction mvebu_has_ioportfunction mvebu_pcie_link_upfunction mvebu_pcie_get_local_bus_nrfunction mvebu_pcie_set_local_bus_nrfunction mvebu_pcie_set_local_dev_nrfunction mvebu_pcie_disable_winsfunction mvebu_pcie_setup_winsfunction mvebu_pcie_setup_hwfunction mvebu_pcie_child_rd_conffunction mvebu_pcie_child_wr_conffunction mvebu_pcie_del_windowsfunction onefunction mvebu_pcie_set_windowfunction mvebu_pcie_handle_iobase_changefunction mvebu_pcie_handle_membase_changefunction mvebu_pci_bridge_emul_base_conf_readfunction mvebu_pci_bridge_emul_pcie_conf_readfunction mvebu_pci_bridge_emul_ext_conf_readfunction mvebu_pci_bridge_emul_base_conf_writefunction mvebu_pci_bridge_emul_pcie_conf_writefunction mvebu_pci_bridge_emul_ext_conf_writefunction mvebu_pci_bridge_emul_initfunction mvebu_pcie_wr_conffunction mvebu_pcie_rd_conffunction mvebu_pcie_intx_irq_maskfunction mvebu_pcie_intx_irq_unmaskfunction mvebu_pcie_intx_irq_mapfunction mvebu_pcie_init_irq_domainfunction mvebu_pcie_irq_handlerfunction mvebu_pcie_map_irqfunction mvebu_pcie_align_resourcefunction mvebu_get_tgt_attrfunction for_each_of_rangefunction mvebu_pcie_suspendfunction mvebu_pcie_resumefunction mvebu_pcie_port_clk_putfunction mvebu_pcie_parse_portfunction mvebu_pcie_powerupfunction mvebu_pcie_powerdownfunction devm_of_pci_get_host_bridge_resourcesfunction mvebu_pcie_probefunction mvebu_pcie_remove
Annotated Snippet
struct mvebu_pcie {
struct platform_device *pdev;
struct mvebu_pcie_port *ports;
struct resource io;
struct resource realio;
struct resource mem;
int nports;
};
struct mvebu_pcie_window {
phys_addr_t base;
phys_addr_t remap;
size_t size;
};
/* Structure representing one PCIe interface */
struct mvebu_pcie_port {
char *name;
void __iomem *base;
u32 port;
u32 lane;
bool is_x4;
int devfn;
unsigned int mem_target;
unsigned int mem_attr;
unsigned int io_target;
unsigned int io_attr;
struct clk *clk;
struct gpio_desc *reset_gpio;
char *reset_name;
struct pci_bridge_emul bridge;
struct device_node *dn;
struct mvebu_pcie *pcie;
struct mvebu_pcie_window memwin;
struct mvebu_pcie_window iowin;
u32 saved_pcie_stat;
struct resource regs;
u8 slot_power_limit_value;
u8 slot_power_limit_scale;
struct irq_domain *intx_irq_domain;
raw_spinlock_t irq_lock;
int intx_irq;
};
static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
{
writel(val, port->base + reg);
}
static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg)
{
return readl(port->base + reg);
}
static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port)
{
return port->io_target != -1 && port->io_attr != -1;
}
static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
{
return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
}
static u8 mvebu_pcie_get_local_bus_nr(struct mvebu_pcie_port *port)
{
return (mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_BUS) >> 8;
}
static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
{
u32 stat;
stat = mvebu_readl(port, PCIE_STAT_OFF);
stat &= ~PCIE_STAT_BUS;
stat |= nr << 8;
mvebu_writel(port, stat, PCIE_STAT_OFF);
}
static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
{
u32 stat;
stat = mvebu_readl(port, PCIE_STAT_OFF);
stat &= ~PCIE_STAT_DEV;
stat |= nr << 16;
mvebu_writel(port, stat, PCIE_STAT_OFF);
}
static void mvebu_pcie_disable_wins(struct mvebu_pcie_port *port)
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/module.h`, `linux/pci.h`, `linux/bitfield.h`, `linux/clk.h`, `linux/delay.h`, `linux/gpio/consumer.h`, `linux/init.h`.
- Detected declarations: `struct mvebu_pcie_port`, `struct mvebu_pcie`, `struct mvebu_pcie_window`, `struct mvebu_pcie_port`, `function mvebu_writel`, `function mvebu_readl`, `function mvebu_has_ioport`, `function mvebu_pcie_link_up`, `function mvebu_pcie_get_local_bus_nr`, `function mvebu_pcie_set_local_bus_nr`.
- Atlas domain: Representative Device Path / PCIe NVMe Storage Path.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.