drivers/pci/controller/pci-tegra.c
Source file repositories/reference/linux-study-clean/drivers/pci/controller/pci-tegra.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/pci/controller/pci-tegra.c- Extension
.c- Size
- 72272 bytes
- Lines
- 2738
- Domain
- Representative Device Path
- Bucket
- PCIe NVMe Storage Path
- Inferred role
- Representative Device Path: implementation source
- Status
- source implementation candidate
Why This File Exists
Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.
- Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/clk.hlinux/cleanup.hlinux/debugfs.hlinux/delay.hlinux/export.hlinux/gpio/consumer.hlinux/interrupt.hlinux/iopoll.hlinux/irq.hlinux/irqchip/chained_irq.hlinux/irqchip/irq-msi-lib.hlinux/irqdomain.hlinux/kernel.hlinux/init.hlinux/module.hlinux/msi.hlinux/of_address.hlinux/of_pci.hlinux/of_platform.hlinux/pci.hlinux/phy/phy.hlinux/pinctrl/consumer.hlinux/platform_device.hlinux/reset.hlinux/sizes.hlinux/slab.hlinux/vmalloc.hlinux/regulator/consumer.hsoc/tegra/cpuidle.hsoc/tegra/pmc.h../pci.h
Detected Declarations
struct tegra_msistruct tegra_pcie_port_socstruct tegra_pcie_socstruct tegra_pciestruct tegra_pcie_portfunction afi_writelfunction afi_readlfunction pads_writelfunction pads_readlfunction addressfunction list_for_each_entryfunction tegra_pcie_config_readfunction tegra_pcie_config_writefunction tegra_pcie_port_get_pex_ctrlfunction tegra_pcie_port_resetfunction tegra_pcie_enable_rp_featuresfunction tegra_pcie_program_ectl_settingsfunction tegra_pcie_apply_sw_fixupfunction tegra_pcie_port_enablefunction tegra_pcie_port_disablefunction tegra_pcie_port_freefunction tegra_pcie_fixup_classfunction tegra_pcie_relax_enablefunction tegra_pcie_map_irqfunction tegra_pcie_isrfunction tegra_pcie_setup_translationsfunction resource_list_for_each_entryfunction tegra_pcie_pll_waitfunction tegra_pcie_phy_enablefunction tegra_pcie_phy_disablefunction tegra_pcie_port_phy_power_onfunction tegra_pcie_port_phy_power_offfunction tegra_pcie_phy_power_onfunction list_for_each_entryfunction tegra_pcie_phy_power_offfunction list_for_each_entryfunction tegra_pcie_enable_controllerfunction list_for_each_entryfunction tegra_pcie_power_offfunction tegra_pcie_power_onfunction tegra_pcie_apply_pad_settingsfunction tegra_pcie_clocks_getfunction tegra_pcie_resets_getfunction tegra_pcie_phys_get_legacyfunction tegra_pcie_port_get_physfunction tegra_pcie_phys_getfunction list_for_each_entryfunction tegra_pcie_phys_put
Annotated Snippet
struct tegra_msi {
DECLARE_BITMAP(used, INT_PCI_MSI_NR);
struct irq_domain *domain;
struct mutex map_lock;
raw_spinlock_t mask_lock;
void *virt;
dma_addr_t phys;
int irq;
};
/* used to differentiate between Tegra SoC generations */
struct tegra_pcie_port_soc {
struct {
u8 turnoff_bit;
u8 ack_bit;
} pme;
};
struct tegra_pcie_soc {
unsigned int num_ports;
const struct tegra_pcie_port_soc *ports;
unsigned int msi_base_shift;
unsigned long afi_pex2_ctrl;
u32 pads_pll_ctl;
u32 tx_ref_sel;
u32 pads_refclk_cfg0;
u32 pads_refclk_cfg1;
u32 update_fc_threshold;
bool has_pex_clkreq_en;
bool has_pex_bias_ctrl;
bool has_intr_prsnt_sense;
bool has_cml_clk;
bool has_gen2;
bool force_pca_enable;
bool program_uphy;
bool update_clamp_threshold;
bool program_deskew_time;
bool update_fc_timer;
bool has_cache_bars;
struct {
struct {
u32 rp_ectl_2_r1;
u32 rp_ectl_4_r1;
u32 rp_ectl_5_r1;
u32 rp_ectl_6_r1;
u32 rp_ectl_2_r2;
u32 rp_ectl_4_r2;
u32 rp_ectl_5_r2;
u32 rp_ectl_6_r2;
} regs;
bool enable;
} ectl;
};
struct tegra_pcie {
struct device *dev;
void __iomem *pads;
void __iomem *afi;
void __iomem *cfg;
int irq;
struct resource cs;
struct clk *pex_clk;
struct clk *afi_clk;
struct clk *pll_e;
struct clk *cml_clk;
struct reset_control *pex_rst;
struct reset_control *afi_rst;
struct reset_control *pcie_xrst;
struct tegra_pmc *pmc;
bool legacy_phy;
struct phy *phy;
struct tegra_msi msi;
struct list_head ports;
u32 xbar_config;
struct regulator_bulk_data *supplies;
unsigned int num_supplies;
const struct tegra_pcie_soc *soc;
struct dentry *debugfs;
};
Annotation
- Immediate include surface: `linux/clk.h`, `linux/cleanup.h`, `linux/debugfs.h`, `linux/delay.h`, `linux/export.h`, `linux/gpio/consumer.h`, `linux/interrupt.h`, `linux/iopoll.h`.
- Detected declarations: `struct tegra_msi`, `struct tegra_pcie_port_soc`, `struct tegra_pcie_soc`, `struct tegra_pcie`, `struct tegra_pcie_port`, `function afi_writel`, `function afi_readl`, `function pads_writel`, `function pads_readl`, `function address`.
- Atlas domain: Representative Device Path / PCIe NVMe Storage Path.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.