drivers/pci/controller/pcie-altera.c

Source file repositories/reference/linux-study-clean/drivers/pci/controller/pcie-altera.c

File Facts

System
Linux kernel
Corpus path
drivers/pci/controller/pcie-altera.c
Extension
.c
Size
27283 bytes
Lines
1066
Domain
Representative Device Path
Bucket
PCIe NVMe Storage Path
Inferred role
Representative Device Path: implementation source
Status
source implementation candidate

Why This File Exists

Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.

Dependency Surface

Detected Declarations

Annotated Snippet

struct altera_pcie {
	struct platform_device	*pdev;
	void __iomem		*cra_base;
	void __iomem		*hip_base;
	int			irq;
	u8			root_bus_nr;
	struct irq_domain	*irq_domain;
	struct resource		bus_range;
	const struct altera_pcie_data	*pcie_data;
};

struct altera_pcie_ops {
	int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value);
	void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *headers,
			      u32 data, bool align);
	bool (*get_link_status)(struct altera_pcie *pcie);
	int (*rp_read_cfg)(struct altera_pcie *pcie, int where,
			   int size, u32 *value);
	int (*rp_write_cfg)(struct altera_pcie *pcie, u8 busno,
			    int where, int size, u32 value);
	int (*ep_read_cfg)(struct altera_pcie *pcie, u8 busno,
			   unsigned int devfn, int where, int size, u32 *value);
	int (*ep_write_cfg)(struct altera_pcie *pcie, u8 busno,
			    unsigned int devfn, int where, int size, u32 value);
	void (*rp_isr)(struct irq_desc *desc);
};

struct altera_pcie_data {
	const struct altera_pcie_ops *ops;
	enum altera_pcie_version version;
	u32 cap_offset;		/* PCIe capability structure register offset */
	u32 cfgrd0;
	u32 cfgrd1;
	u32 cfgwr0;
	u32 cfgwr1;
	u32 port_conf_offset;
	u32 port_irq_status_offset;
	u32 port_irq_enable_offset;
};

struct tlp_rp_regpair_t {
	u32 ctrl;
	u32 reg0;
	u32 reg1;
};

static inline void cra_writel(struct altera_pcie *pcie, const u32 value,
			      const u32 reg)
{
	writel_relaxed(value, pcie->cra_base + reg);
}

static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
{
	return readl_relaxed(pcie->cra_base + reg);
}

static inline void cra_writew(struct altera_pcie *pcie, const u32 value,
			      const u32 reg)
{
	writew_relaxed(value, pcie->cra_base + reg);
}

static inline u32 cra_readw(struct altera_pcie *pcie, const u32 reg)
{
	return readw_relaxed(pcie->cra_base + reg);
}

static inline void cra_writeb(struct altera_pcie *pcie, const u32 value,
			      const u32 reg)
{
	writeb_relaxed(value, pcie->cra_base + reg);
}

static inline u32 cra_readb(struct altera_pcie *pcie, const u32 reg)
{
	return readb_relaxed(pcie->cra_base + reg);
}

static bool altera_pcie_link_up(struct altera_pcie *pcie)
{
	return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
}

static bool s10_altera_pcie_link_up(struct altera_pcie *pcie)
{
	void __iomem *addr = S10_RP_CFG_ADDR(pcie,
				   pcie->pcie_data->cap_offset +
				   PCI_EXP_LNKSTA);

Annotation

Implementation Notes