drivers/pci/controller/pcie-rzg3s-host.c

Source file repositories/reference/linux-study-clean/drivers/pci/controller/pcie-rzg3s-host.c

File Facts

System
Linux kernel
Corpus path
drivers/pci/controller/pcie-rzg3s-host.c
Extension
.c
Size
54897 bytes
Lines
1948
Domain
Representative Device Path
Bucket
PCIe NVMe Storage Path
Inferred role
Representative Device Path: implementation source
Status
source implementation candidate

Why This File Exists

Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.

Dependency Surface

Detected Declarations

Annotated Snippet

struct rzg3s_sysc_function {
	u32 offset;
	u32 mask;
};

/**
 * enum rzg3s_sysc_func_id - System controller function IDs
 * @RZG3S_SYSC_FUNC_ID_RST_RSM_B: RST_RSM_B SYSC function ID
 * @RZG3S_SYSC_FUNC_ID_L1_ALLOW: L1 allow SYSC function ID
 * @RZG3S_SYSC_FUNC_ID_MODE: Mode SYSC function ID
 * @RZG3S_SYSC_FUNC_ID_MAX: Max SYSC function ID
 */
enum rzg3s_sysc_func_id {
	RZG3S_SYSC_FUNC_ID_RST_RSM_B,
	RZG3S_SYSC_FUNC_ID_L1_ALLOW,
	RZG3S_SYSC_FUNC_ID_MODE,
	RZG3S_SYSC_FUNC_ID_MAX,
};

/**
 * struct rzg3s_sysc_info - RZ/G3S System Controller info
 * @functions: SYSC function descriptors array
 */
struct rzg3s_sysc_info {
	const struct rzg3s_sysc_function functions[RZG3S_SYSC_FUNC_ID_MAX];
};

/**
 * struct rzg3s_sysc - RZ/G3S System Controller descriptor
 * @regmap: System controller regmap
 * @info: System controller info
 */
struct rzg3s_sysc {
	struct regmap *regmap;
	const struct rzg3s_sysc_info *info;
};

/**
 * struct rzg3s_pcie_msi - RZ/G3S PCIe MSI data structure
 * @domain: IRQ domain
 * @map: bitmap with the allocated MSIs
 * @dma_addr: address of the allocated MSI window
 * @window_base: base address of the MSI window
 * @pages: allocated pages for MSI window mapping
 * @map_lock: lock for bitmap with the allocated MSIs
 * @irq: MSI interrupt
 */
struct rzg3s_pcie_msi {
	struct irq_domain *domain;
	DECLARE_BITMAP(map, RZG3S_PCI_MSI_INT_NR);
	dma_addr_t dma_addr;
	dma_addr_t window_base;
	unsigned long pages;
	struct mutex map_lock;
	int irq;
};

struct rzg3s_pcie_host;

/**
 * struct rzg3s_pcie_soc_data - SoC specific data
 * @init_phy: PHY initialization function
 * @config_pre_init: Optional callback for SoC-specific pre-configuration
 * @config_post_init: Callback for SoC-specific post-configuration
 * @config_deinit: Callback for SoC-specific de-initialization
 * @power_resets: array with the resets that need to be de-asserted after
 *                power-on
 * @cfg_resets: array with the resets that need to be de-asserted after
 *              configuration
 * @sysc_info: SYSC info
 * @num_power_resets: number of power resets
 * @num_cfg_resets: number of configuration resets
 */
struct rzg3s_pcie_soc_data {
	int (*init_phy)(struct rzg3s_pcie_host *host);
	void (*config_pre_init)(struct rzg3s_pcie_host *host);
	int (*config_post_init)(struct rzg3s_pcie_host *host);
	int (*config_deinit)(struct rzg3s_pcie_host *host);
	const char * const *power_resets;
	const char * const *cfg_resets;
	struct rzg3s_sysc_info sysc_info;
	u8 num_power_resets;
	u8 num_cfg_resets;
};

/**
 * struct rzg3s_pcie_port - RZ/G3S PCIe Root Port data structure
 * @refclk: PCIe reference clock
 * @vendor_id: Vendor ID
 * @device_id: Device ID

Annotation

Implementation Notes