drivers/pci/controller/pcie-xilinx-common.h

File Facts

System

Linux kernel

Corpus path

drivers/pci/controller/pcie-xilinx-common.h

Extension

.h

Size

1041 bytes

Lines

32

Domain

Representative Device Path

Bucket

PCIe NVMe Storage Path

Inferred role

Representative Device Path: implementation source

Status

source implementation candidate

Why This File Exists

Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.

• Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.
• Touches IRQ or DMA behavior; this matters for the representative real-device path.

Dependency Surface

• linux/pci.h
• linux/pci-ecam.h
• linux/platform_device.h

Detected Declarations

• No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#include <linux/pci.h>
#include <linux/pci-ecam.h>
#include <linux/platform_device.h>

/* Interrupt registers definitions */
#define XILINX_PCIE_INTR_LINK_DOWN		0
#define XILINX_PCIE_INTR_HOT_RESET		3
#define XILINX_PCIE_INTR_CFG_PCIE_TIMEOUT	4
#define XILINX_PCIE_INTR_CFG_TIMEOUT		8
#define XILINX_PCIE_INTR_CORRECTABLE		9
#define XILINX_PCIE_INTR_NONFATAL		10
#define XILINX_PCIE_INTR_FATAL			11
#define XILINX_PCIE_INTR_CFG_ERR_POISON		12
#define XILINX_PCIE_INTR_PME_TO_ACK_RCVD	15
#define XILINX_PCIE_INTR_INTX			16
#define XILINX_PCIE_INTR_PM_PME_RCVD		17
#define XILINX_PCIE_INTR_MSI			17
#define XILINX_PCIE_INTR_SLV_UNSUPP		20
#define XILINX_PCIE_INTR_SLV_UNEXP		21
#define XILINX_PCIE_INTR_SLV_COMPL		22
#define XILINX_PCIE_INTR_SLV_ERRP		23
#define XILINX_PCIE_INTR_SLV_CMPABT		24
#define XILINX_PCIE_INTR_SLV_ILLBUR		25
#define XILINX_PCIE_INTR_MST_DECERR		26
#define XILINX_PCIE_INTR_MST_SLVERR		27
#define XILINX_PCIE_INTR_SLV_PCIE_TIMEOUT	28

Annotation

• Immediate include surface: `linux/pci.h`, `linux/pci-ecam.h`, `linux/platform_device.h`.
• Atlas domain: Representative Device Path / PCIe NVMe Storage Path.
• Implementation status: source implementation candidate.
• IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.