drivers/pci/controller/plda/pcie-plda-host.c
Source file repositories/reference/linux-study-clean/drivers/pci/controller/plda/pcie-plda-host.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/pci/controller/plda/pcie-plda-host.c- Extension
.c- Size
- 17470 bytes
- Lines
- 652
- Domain
- Representative Device Path
- Bucket
- PCIe NVMe Storage Path
- Inferred role
- Representative Device Path: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.
- Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/align.hlinux/bitfield.hlinux/irqchip/chained_irq.hlinux/irqchip/irq-msi-lib.hlinux/irqdomain.hlinux/msi.hlinux/pci_regs.hlinux/pci-ecam.hlinux/wordpart.hpcie-plda.h
Detected Declarations
function Copyrightfunction plda_handle_msifunction for_each_set_bitfunction plda_msi_bottom_irq_ackfunction plda_compose_msi_msgfunction plda_irq_msi_domain_allocfunction plda_irq_msi_domain_freefunction plda_allocate_msi_domainsfunction plda_handle_intxfunction for_each_set_bitfunction plda_ack_intx_irqfunction plda_mask_intx_irqfunction plda_unmask_intx_irqfunction plda_pcie_intx_mapfunction plda_get_eventsfunction plda_event_handlerfunction plda_handle_eventfunction plda_hwirq_to_maskfunction plda_ack_event_irqfunction plda_mask_event_irqfunction plda_unmask_event_irqfunction plda_pcie_event_mapfunction plda_pcie_init_irq_domainsfunction plda_init_interruptsfunction for_each_set_bitfunction plda_pcie_setup_windowfunction plda_pcie_setup_inbound_address_translationfunction plda_pcie_setup_iomemsfunction resource_list_for_each_entryfunction plda_pcie_irq_domain_deinitfunction plda_pcie_host_initfunction plda_pcie_host_deinitexport plda_pcie_map_busexport plda_init_interruptsexport plda_pcie_setup_windowexport plda_pcie_setup_inbound_address_translationexport plda_pcie_setup_iomemsexport plda_pcie_host_initexport plda_pcie_host_deinit
Annotated Snippet
for_each_set_bit(bit, &status, msi->num_vectors) {
ret = generic_handle_domain_irq(msi->dev_domain, bit);
if (ret)
dev_err_ratelimited(dev, "bad MSI IRQ %d\n",
bit);
}
}
chained_irq_exit(chip, desc);
}
static void plda_msi_bottom_irq_ack(struct irq_data *data)
{
struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
void __iomem *bridge_base_addr = port->bridge_addr;
u32 bitpos = data->hwirq;
writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI);
}
static void plda_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
{
struct plda_pcie_rp *port = irq_data_get_irq_chip_data(data);
phys_addr_t addr = port->msi.vector_phy;
msg->address_lo = lower_32_bits(addr);
msg->address_hi = upper_32_bits(addr);
msg->data = data->hwirq;
dev_dbg(port->dev, "msi#%x address_hi %#x address_lo %#x\n",
(int)data->hwirq, msg->address_hi, msg->address_lo);
}
static struct irq_chip plda_msi_bottom_irq_chip = {
.name = "PLDA MSI",
.irq_ack = plda_msi_bottom_irq_ack,
.irq_compose_msi_msg = plda_compose_msi_msg,
};
static int plda_irq_msi_domain_alloc(struct irq_domain *domain,
unsigned int virq,
unsigned int nr_irqs,
void *args)
{
struct plda_pcie_rp *port = domain->host_data;
struct plda_msi *msi = &port->msi;
unsigned long bit;
mutex_lock(&msi->lock);
bit = find_first_zero_bit(msi->used, msi->num_vectors);
if (bit >= msi->num_vectors) {
mutex_unlock(&msi->lock);
return -ENOSPC;
}
set_bit(bit, msi->used);
irq_domain_set_info(domain, virq, bit, &plda_msi_bottom_irq_chip,
domain->host_data, handle_edge_irq, NULL, NULL);
mutex_unlock(&msi->lock);
return 0;
}
static void plda_irq_msi_domain_free(struct irq_domain *domain,
unsigned int virq,
unsigned int nr_irqs)
{
struct irq_data *d = irq_domain_get_irq_data(domain, virq);
struct plda_pcie_rp *port = irq_data_get_irq_chip_data(d);
struct plda_msi *msi = &port->msi;
mutex_lock(&msi->lock);
if (test_bit(d->hwirq, msi->used))
__clear_bit(d->hwirq, msi->used);
else
dev_err(port->dev, "trying to free unused MSI%lu\n", d->hwirq);
mutex_unlock(&msi->lock);
}
static const struct irq_domain_ops msi_domain_ops = {
.alloc = plda_irq_msi_domain_alloc,
.free = plda_irq_msi_domain_free,
};
#define PLDA_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \
MSI_FLAG_USE_DEF_CHIP_OPS | \
Annotation
- Immediate include surface: `linux/align.h`, `linux/bitfield.h`, `linux/irqchip/chained_irq.h`, `linux/irqchip/irq-msi-lib.h`, `linux/irqdomain.h`, `linux/msi.h`, `linux/pci_regs.h`, `linux/pci-ecam.h`.
- Detected declarations: `function Copyright`, `function plda_handle_msi`, `function for_each_set_bit`, `function plda_msi_bottom_irq_ack`, `function plda_compose_msi_msg`, `function plda_irq_msi_domain_alloc`, `function plda_irq_msi_domain_free`, `function plda_allocate_msi_domains`, `function plda_handle_intx`, `function for_each_set_bit`.
- Atlas domain: Representative Device Path / PCIe NVMe Storage Path.
- Implementation status: integration implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.