drivers/pci/hotplug/ibmphp.h

File Facts

System

Linux kernel

Corpus path

drivers/pci/hotplug/ibmphp.h

Extension

.h

Size

23674 bytes

Lines

750

Domain

Representative Device Path

Bucket

PCIe NVMe Storage Path

Inferred role

Representative Device Path: implementation source

Status

source implementation candidate

Why This File Exists

Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.

• Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• linux/pci_hotplug.h
• linux/pci_regs.h

Detected Declarations

• struct rio_table_hdr
• struct scal_detail
• struct rio_detail
• struct opt_rio
• struct opt_rio_lo
• struct ebda_hpc_list
• struct ebda_hpc_slot
• struct ebda_hpc_bus
• struct isa_ctlr_access
• struct pci_ctlr_access
• struct wpeg_i2c_ctlr_access
• struct ebda_rsrc_list
• struct ebda_pci_rsrc
• struct bus_info
• struct range_node
• struct bus_node
• struct resource_node
• struct res_needed
• struct pci_func
• struct slot
• struct controller

Annotated Snippet

struct rio_table_hdr {
	u8 ver_num;
	u8 scal_count;
	u8 riodev_count;
	u16 offset;
};

//-------------------------------------------------------------
// SCALABILITY DETAIL
//-------------------------------------------------------------

struct scal_detail {
	u8 node_id;
	u32 cbar;
	u8 port0_node_connect;
	u8 port0_port_connect;
	u8 port1_node_connect;
	u8 port1_port_connect;
	u8 port2_node_connect;
	u8 port2_port_connect;
	u8 chassis_num;
//	struct list_head scal_detail_list;
};

//--------------------------------------------------------------
// RIO DETAIL
//--------------------------------------------------------------

struct rio_detail {
	u8 rio_node_id;
	u32 bbar;
	u8 rio_type;
	u8 owner_id;
	u8 port0_node_connect;
	u8 port0_port_connect;
	u8 port1_node_connect;
	u8 port1_port_connect;
	u8 first_slot_num;
	u8 status;
	u8 wpindex;
	u8 chassis_num;
	struct list_head rio_detail_list;
};

struct opt_rio {
	u8 rio_type;
	u8 chassis_num;
	u8 first_slot_num;
	u8 middle_num;
	struct list_head opt_rio_list;
};

struct opt_rio_lo {
	u8 rio_type;
	u8 chassis_num;
	u8 first_slot_num;
	u8 middle_num;
	u8 pack_count;
	struct list_head opt_rio_lo_list;
};

/****************************************************************
*  HPC DESCRIPTOR NODE                                          *
****************************************************************/

struct ebda_hpc_list {
	u8 format;
	u16 num_ctlrs;
	short phys_addr;
//      struct list_head ebda_hpc_list;
};
/*****************************************************************
*   IN HPC DATA STRUCTURE, THE ASSOCIATED SLOT AND BUS           *
*   STRUCTURE                                                    *
*****************************************************************/

struct ebda_hpc_slot {
	u8 slot_num;
	u32 slot_bus_num;
	u8 ctl_index;
	u8 slot_cap;
};

struct ebda_hpc_bus {
	u32 bus_num;
	u8 slots_at_33_conv;
	u8 slots_at_66_conv;
	u8 slots_at_66_pcix;
	u8 slots_at_100_pcix;
	u8 slots_at_133_pcix;

Annotation

• Immediate include surface: `linux/pci_hotplug.h`, `linux/pci_regs.h`.
• Detected declarations: `struct rio_table_hdr`, `struct scal_detail`, `struct rio_detail`, `struct opt_rio`, `struct opt_rio_lo`, `struct ebda_hpc_list`, `struct ebda_hpc_slot`, `struct ebda_hpc_bus`, `struct isa_ctlr_access`, `struct pci_ctlr_access`.
• Atlas domain: Representative Device Path / PCIe NVMe Storage Path.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.