drivers/pci/pcie/aer_inject.c
Source file repositories/reference/linux-study-clean/drivers/pci/pcie/aer_inject.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/pci/pcie/aer_inject.c- Extension
.c- Size
- 12965 bytes
- Lines
- 549
- Domain
- Representative Device Path
- Bucket
- PCIe NVMe Storage Path
- Inferred role
- Representative Device Path: operation-table or driver-model contract
- Status
- pattern implementation candidate
Why This File Exists
Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.
- Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.
- Defines an operation table; this is where Linux turns generic core objects into subsystem-specific behavior.
- Touches user memory; correctness depends on fault-safe copying and privilege boundary handling.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/module.hlinux/init.hlinux/interrupt.hlinux/miscdevice.hlinux/pci.hlinux/slab.hlinux/fs.hlinux/uaccess.hlinux/stddef.hlinux/device.hportdrv.h
Detected Declarations
struct aer_error_injstruct aer_errorstruct pci_bus_opsfunction aer_error_initfunction list_for_each_entryfunction list_for_each_entryfunction aer_inj_readfunction aer_inj_writefunction aer_inj_read_configfunction aer_inj_write_configfunction pci_bus_ops_initfunction pci_bus_set_aer_opsfunction aer_injectfunction aer_inject_writefunction aer_inject_initfunction aer_inject_exitmodule init aer_inject_init
Annotated Snippet
static const struct file_operations aer_inject_fops = {
.write = aer_inject_write,
.owner = THIS_MODULE,
.llseek = noop_llseek,
};
static struct miscdevice aer_inject_device = {
.minor = MISC_DYNAMIC_MINOR,
.name = "aer_inject",
.fops = &aer_inject_fops,
};
static int __init aer_inject_init(void)
{
return misc_register(&aer_inject_device);
}
static void __exit aer_inject_exit(void)
{
struct aer_error *err, *err_next;
unsigned long flags;
struct pci_bus_ops *bus_ops;
misc_deregister(&aer_inject_device);
while ((bus_ops = pci_bus_ops_pop())) {
pci_bus_set_ops(bus_ops->bus, bus_ops->ops);
kfree(bus_ops);
}
spin_lock_irqsave(&inject_lock, flags);
list_for_each_entry_safe(err, err_next, &einjected, list) {
list_del(&err->list);
kfree(err);
}
spin_unlock_irqrestore(&inject_lock, flags);
}
module_init(aer_inject_init);
module_exit(aer_inject_exit);
MODULE_DESCRIPTION("PCIe AER software error injector");
MODULE_LICENSE("GPL");
Annotation
- Immediate include surface: `linux/module.h`, `linux/init.h`, `linux/interrupt.h`, `linux/miscdevice.h`, `linux/pci.h`, `linux/slab.h`, `linux/fs.h`, `linux/uaccess.h`.
- Detected declarations: `struct aer_error_inj`, `struct aer_error`, `struct pci_bus_ops`, `function aer_error_init`, `function list_for_each_entry`, `function list_for_each_entry`, `function aer_inj_read`, `function aer_inj_write`, `function aer_inj_read_config`, `function aer_inj_write_config`.
- Atlas domain: Representative Device Path / PCIe NVMe Storage Path.
- Implementation status: pattern implementation candidate.
- This snippet crosses the user/kernel memory boundary; validate fault handling and access checks before translating the pattern.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.