drivers/pci/probe.c
Source file repositories/reference/linux-study-clean/drivers/pci/probe.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/pci/probe.c- Extension
.c- Size
- 94564 bytes
- Lines
- 3586
- Domain
- Representative Device Path
- Bucket
- PCIe NVMe Storage Path
- Inferred role
- Representative Device Path: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.
- Part of the selected hardware vertical slice: PCI discovery, driver binding, NVMe queues, block requests, DMA, interrupts, and completion.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/array_size.hlinux/kernel.hlinux/delay.hlinux/init.hlinux/pci.hlinux/msi.hlinux/of_pci.hlinux/of_platform.hlinux/platform_device.hlinux/pci_hotplug.hlinux/slab.hlinux/sprintf.hlinux/module.hlinux/cpumask.hlinux/aer.hlinux/acpi.hlinux/hypervisor.hlinux/irqdomain.hlinux/pm_runtime.hlinux/bitfield.htrace/events/pci.hpci.h
Detected Declarations
struct pci_domain_busn_resfunction release_pcibus_devfunction pcibus_class_initfunction pci_sizefunction decode_barfunction __pci_size_barsfunction __pci_size_stdbarsfunction __pci_size_romfunction __pci_read_basefunction addressfunction pci_read_basesfunction pci_read_bridge_iofunction pci_read_bridge_mmiofunction pci_read_bridge_mmio_preffunction pci_read_bridge_windowsfunction pci_read_bridge_basesfunction pci_bus_for_each_resourcefunction pci_release_host_bridge_devfunction pci_init_host_bridgefunction devm_pci_alloc_host_bridge_releasefunction pci_free_host_bridgefunction valuefunction pcie_update_link_speedfunction agp_speedfunction pci_set_bus_speedfunction pci_set_bus_msi_domainfunction pci_preserve_configfunction pci_register_host_bridgefunction pci_bridge_child_ext_cfg_accessiblefunction pci_enable_rrs_svfunction pbus_validate_busnfunction pci_ea_fixed_busnrsfunction pci_scan_bridge_extendfunction pci_scan_bridgefunction pci_read_irqfunction set_pcie_port_typefunction set_pcie_hotplug_bridgefunction set_pcie_thunderboltfunction set_pcie_cxlfunction set_pcie_untrustedfunction pci_set_removablefunction Wefunction pci_ext_cfg_is_aliasedfunction pci_cfg_space_size_extfunction pci_cfg_space_sizefunction pci_classfunction pci_subsystem_idsfunction pci_hdr_type
Annotated Snippet
err = device_add(&bridge->dev);
if (err)
goto free;
bus->bridge = get_device(&bridge->dev);
device_enable_async_suspend(bus->bridge);
pci_set_bus_of_node(bus);
pci_set_bus_msi_domain(bus);
if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) &&
!pci_host_of_has_msi_map(parent))
bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
if (!parent)
set_dev_node(bus->bridge, pcibus_to_node(bus));
bus->dev.class = &pcibus_class;
bus->dev.parent = bus->bridge;
dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
name = dev_name(&bus->dev);
err = device_register(&bus->dev);
bus_registered = true;
if (err)
goto unregister;
pcibios_add_bus(bus);
if (bus->ops->add_bus) {
err = bus->ops->add_bus(bus);
if (WARN_ON(err < 0))
dev_err(&bus->dev, "failed to add bus: %d\n", err);
}
/* Create legacy_io and legacy_mem files for this bus */
pci_create_legacy_files(bus);
if (parent)
dev_info(parent, "PCI host bridge to bus %s\n", name);
else
pr_info("PCI host bridge to bus %s\n", name);
if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE)
dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n");
/* Check if the boot configuration by FW needs to be preserved */
bridge->preserve_config = pci_preserve_config(bridge);
/* Coalesce contiguous windows */
resource_list_for_each_entry_safe(window, n, &resources) {
if (list_is_last(&window->node, &resources))
break;
next = list_next_entry(window, node);
offset = window->offset;
res = window->res;
next_offset = next->offset;
next_res = next->res;
if (res->flags != next_res->flags || offset != next_offset)
continue;
if (res->end + 1 == next_res->start) {
next_res->start = res->start;
res->flags = res->start = res->end = 0;
}
}
/* Add initial resources to the bus */
resource_list_for_each_entry_safe(window, n, &resources) {
offset = window->offset;
res = window->res;
if (!res->flags && !res->start && !res->end) {
release_resource(res);
resource_list_destroy_entry(window);
continue;
}
list_move_tail(&window->node, &bridge->windows);
if (res->flags & IORESOURCE_BUS)
pci_bus_insert_busn_res(bus, bus->number, res->end);
else
pci_bus_add_resource(bus, res);
if (offset) {
if (resource_type(res) == IORESOURCE_IO)
fmt = " (bus address [%#06llx-%#06llx])";
else
fmt = " (bus address [%#010llx-%#010llx])";
Annotation
- Immediate include surface: `linux/array_size.h`, `linux/kernel.h`, `linux/delay.h`, `linux/init.h`, `linux/pci.h`, `linux/msi.h`, `linux/of_pci.h`, `linux/of_platform.h`.
- Detected declarations: `struct pci_domain_busn_res`, `function release_pcibus_dev`, `function pcibus_class_init`, `function pci_size`, `function decode_bar`, `function __pci_size_bars`, `function __pci_size_stdbars`, `function __pci_size_rom`, `function __pci_read_base`, `function address`.
- Atlas domain: Representative Device Path / PCIe NVMe Storage Path.
- Implementation status: integration implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.