drivers/perf/arm_v7_pmu.c

Source file repositories/reference/linux-study-clean/drivers/perf/arm_v7_pmu.c

File Facts

System
Linux kernel
Corpus path
drivers/perf/arm_v7_pmu.c
Extension
.c
Size
62440 bytes
Lines
1925
Domain
Driver Families
Bucket
drivers/perf
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code.
 *
 * ARMv7 support: Jean Pihet <jpihet@mvista.com>
 * 2010 (c) MontaVista Software, LLC.
 *
 * Copied from ARMv6 code, with the low level code inspired
 *  by the ARMv7 Oprofile code.
 *
 * Cortex-A8 has up to 4 configurable performance counters and
 *  a single cycle counter.
 * Cortex-A9 has up to 31 configurable performance counters and
 *  a single cycle counter.
 *
 * All counters can be enabled/disabled and IRQ masked separately. The cycle
 *  counter and all 4 performance counters together can be reset separately.
 */

#include <asm/cp15.h>
#include <asm/cputype.h>
#include <asm/irq_regs.h>
#include <asm/vfp.h>
#include "../vfp/vfpinstr.h"

#include <linux/of.h>
#include <linux/perf/arm_pmu.h>
#include <linux/platform_device.h>

/*
 * Common ARMv7 event types
 *
 * Note: An implementation may not be able to count all of these events
 * but the encodings are considered to be `reserved' in the case that
 * they are not available.
 */
#define ARMV7_PERFCTR_PMNC_SW_INCR			0x00
#define ARMV7_PERFCTR_L1_ICACHE_REFILL			0x01
#define ARMV7_PERFCTR_ITLB_REFILL			0x02
#define ARMV7_PERFCTR_L1_DCACHE_REFILL			0x03
#define ARMV7_PERFCTR_L1_DCACHE_ACCESS			0x04
#define ARMV7_PERFCTR_DTLB_REFILL			0x05
#define ARMV7_PERFCTR_MEM_READ				0x06
#define ARMV7_PERFCTR_MEM_WRITE				0x07
#define ARMV7_PERFCTR_INSTR_EXECUTED			0x08
#define ARMV7_PERFCTR_EXC_TAKEN				0x09
#define ARMV7_PERFCTR_EXC_EXECUTED			0x0A
#define ARMV7_PERFCTR_CID_WRITE				0x0B

/*
 * ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
 * It counts:
 *  - all (taken) branch instructions,
 *  - instructions that explicitly write the PC,
 *  - exception generating instructions.
 */
#define ARMV7_PERFCTR_PC_WRITE				0x0C
#define ARMV7_PERFCTR_PC_IMM_BRANCH			0x0D
#define ARMV7_PERFCTR_PC_PROC_RETURN			0x0E
#define ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS		0x0F
#define ARMV7_PERFCTR_PC_BRANCH_MIS_PRED		0x10
#define ARMV7_PERFCTR_CLOCK_CYCLES			0x11
#define ARMV7_PERFCTR_PC_BRANCH_PRED			0x12

/* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */
#define ARMV7_PERFCTR_MEM_ACCESS			0x13
#define ARMV7_PERFCTR_L1_ICACHE_ACCESS			0x14
#define ARMV7_PERFCTR_L1_DCACHE_WB			0x15
#define ARMV7_PERFCTR_L2_CACHE_ACCESS			0x16
#define ARMV7_PERFCTR_L2_CACHE_REFILL			0x17
#define ARMV7_PERFCTR_L2_CACHE_WB			0x18
#define ARMV7_PERFCTR_BUS_ACCESS			0x19
#define ARMV7_PERFCTR_MEM_ERROR				0x1A
#define ARMV7_PERFCTR_INSTR_SPEC			0x1B
#define ARMV7_PERFCTR_TTBR_WRITE			0x1C
#define ARMV7_PERFCTR_BUS_CYCLES			0x1D

#define ARMV7_PERFCTR_CPU_CYCLES			0xFF

/* ARMv7 Cortex-A8 specific event types */
#define ARMV7_A8_PERFCTR_L2_CACHE_ACCESS		0x43
#define ARMV7_A8_PERFCTR_L2_CACHE_REFILL		0x44
#define ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS		0x50
#define ARMV7_A8_PERFCTR_STALL_ISIDE			0x56

/* ARMv7 Cortex-A9 specific event types */
#define ARMV7_A9_PERFCTR_INSTR_CORE_RENAME		0x68
#define ARMV7_A9_PERFCTR_STALL_ICACHE			0x60
#define ARMV7_A9_PERFCTR_STALL_DISPATCH			0x66

Annotation

Implementation Notes